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48 条记录 (耗时 0.032 秒)

    Process for manufacturing an integrated CMOS circuit
    3.
    发明授权
    Process for manufacturing an integrated CMOS circuit 失效
    用于制造集成CMOS电路的工艺

    公开(公告)号：US5882965A

    公开(公告)日：1999-03-16

    申请号：US983263

    申请日：1998-01-09

    申请人： Udo Schwalke ,  Martin Kerber

    发明人： Udo Schwalke ,  Martin Kerber

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

    CPC分类号： H01L21/823842

    摘要： In the production of a dual work function CMOS circuit, a polysilicon layer is produced for the purpose of forming a gate structure, the average grain diameter of which polysilicon layer is greater than the minimum extent in the gate structure, in order to suppress lateral dopant diffusion. In particular, a constriction having a width less than the average grain diameter is produced in the gate structure.

    摘要翻译： PCT No.PCT / DE96 / 01202 Sec。 371日期1998年1月9日 102（e）1998年1月9日PCT PCT 1996年7月4日PCT公布。 公开号WO97 / 03462 日期1997年1月30日在双功能功能CMOS电路的制造中，为了形成栅极结构而制造多晶硅层，其多晶硅层的平均晶粒直径大于栅极结构中的最小程度， 以抑制横向掺杂剂扩散。 特别地，在栅极结构中产生具有小于平均晶粒直径的宽度的收缩。

    Integrated circuit device with current measurement
    6.
    发明申请
    Integrated circuit device with current measurement 审中-公开
    具有电流测量的集成电路器件

    公开(公告)号：US20080042681A1

    公开(公告)日：2008-02-21

    申请号：US11502924

    申请日：2006-08-11

    申请人： Martin Kerber

    发明人： Martin Kerber

    IPC分类号： G01R31/26

    CPC分类号： G01R19/16552

    摘要： An integrated circuit device includes a plurality of transistors having gate dielectrics forming logic for the integrated circuit device, a voltage supply line connected to the transistors, and a current measurement device determining when the current in the voltage supply line exceeds a threshold.

    摘要翻译： 集成电路器件包括多个晶体管，其具有形成用于集成电路器件的逻辑的栅极电介质，连接到晶体管的电压供应线，以及电流测量器件，确定电压提供线上的电流何时超过阈值。

    Semiconductor wafer having a dielectric reliability test structure, integrated circuit product and test method
    7.
    发明申请
    Semiconductor wafer having a dielectric reliability test structure, integrated circuit product and test method 有权
    具有介电可靠性测试结构，集成电路产品和测试方法的半导体晶片

    公开(公告)号：US20070252611A1

    公开(公告)日：2007-11-01

    申请号：US11412548

    申请日：2006-04-27

    申请人： Martin Kerber

    发明人： Martin Kerber

    IPC分类号： G01R31/02

    CPC分类号： G01R31/2884 ,  G01R31/2831 ,  H01L22/34

    摘要： A semiconductor wafer includes a dielectric test structure including a voltage line, a control line, and a plurality of test devices connected in parallel to the voltage line and the control line. Each test device includes a voltage-controlled resistor connected to the control line and a dielectric device, the dielectric device being connected to the voltage line via the voltage-controlled resistor. A method for dielectric reliability testing and forming an integrated circuit product is also provided, as is a wafer with a control voltage pad and an integrated circuit product.

    摘要翻译： 半导体晶片包括电介质测试结构，其包括电压线，控制线和与电压线和控制线并联连接的多个测试装置。 每个测试装置包括连接到控制线的压控电阻器和电介质器件，该电介质器件通过压控电阻器连接到电压线。 还提供了用于介电可靠性测试和形成集成电路产品的方法，以及具有控制电压焊盘和集成电路产品的晶片。

    Method for producing very small structural widths on a semiconductor substrate
    8.
    发明授权
    Method for producing very small structural widths on a semiconductor substrate 失效
    在半导体衬底上制造非常小的结构宽度的方法

    公开(公告)号：US6027972A

    公开(公告)日：2000-02-22

    申请号：US44533

    申请日：1998-03-19

    申请人： Martin Kerber

    发明人： Martin Kerber

    IPC分类号： H01L21/28 ,  H01L21/033 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336

    CPC分类号： H01L27/11517 ,  H01L21/0337 ,  H01L21/0338

    摘要： Very narrow structures are produced on a semiconductor substrate. A first layer deposited over an edge of a structure is anisotropically etched back. The spacer at the edge of the structure which remains after the first layer and the structure are removed, after further deposition and etching steps, finally defines the position and width of the resulting microstructure. The very narrow structure may be the channel width of a flash memory cell.

    摘要翻译： 在半导体衬底上产生非常窄的结构。 沉积在结构边缘上的第一层被各向异性地回蚀刻。 在进一步沉积和蚀刻步骤之后，在第一层和结构之后残留的结构边缘处的间隔物最终限定所得微结构的位置和宽度。 非常窄的结构可以是闪存单元的通道宽度。

    Memory cell and method for producing the memory cell
    9.
    发明授权
    Memory cell and method for producing the memory cell 失效
    用于产生存储单元的存储单元和方法

    公开(公告)号：US5976932A

    公开(公告)日：1999-11-02

    申请号：US884770

    申请日：1997-06-30

    申请人： Martin Kerber

    发明人： Martin Kerber

    IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/266

    CPC分类号： H01L29/66825 ,  H01L29/42324 ,  H01L29/7883

    摘要： A memory cell and a method for producing the memory cell have a plurality of structured layers disposed on a semiconducting base body and an exactly defined overlap region of a first doped region and a floating gate layer. A control gate layer is disposed approximately without any overlap over the first doped region. The memory cell can be programmed with the aid of the Fowler-Nordheim tunnel effect.

    摘要翻译： 存储单元和用于制造存储单元的方法具有设置在半导体基体上的多个结构化层和第一掺杂区域和浮栅层的精确限定的重叠区域。 控制栅极层在第一掺杂区域上大致没有重叠地布置。 借助于Fowler-Nordheim隧道效应可以对存储单元进行编程。

    Integrated switching circuit with CMOS circuit and method for producing isolated active regions of a CMOS circuit
    10.
    发明授权
    Integrated switching circuit with CMOS circuit and method for producing isolated active regions of a CMOS circuit 失效
    具有CMOS电路的集成开关电路和用于产生CMOS电路的隔离有源区的方法

    公开(公告)号：US5847433A

    公开(公告)日：1998-12-08

    申请号：US681296

    申请日：1996-07-22

    申请人： Martin Kerber

    发明人： Martin Kerber

    IPC分类号： H01L21/76 ,  H01L21/765 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/76

    CPC分类号： H01L21/765 ,  H01L27/0928

    摘要： In an integrated switching circuit with a CMOS circuit and a method for producing isolated active regions of the CMOS circuit, a field plate is doped jointly with wells located beneath it, so that the field plate includes an n-doped region and a p-doped region, and a boundary layer forms in a transition region. Upon electrical connection of the field plate regions with the particular well located beneath them, a flat band condition prevails at a substrate surface.

    摘要翻译： 在具有CMOS电路的集成开关电路和用于产生CMOS电路的隔离有源区的方法中，场板与位于其下面的阱一起掺杂，使得场板包括n掺杂区和p掺杂 区域，并且在过渡区域中形成边界层。 在场板区域与位于其下方的特定井的电连接之后，在衬底表面上存在平坦带状条件。