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    Semiconductor integrated circuit having logi gates
    6.
    发明授权
    Semiconductor integrated circuit having logi gates 失效
    具有逻辑门的半导体集成电路

    公开(公告)号：US5675548A

    公开(公告)日：1997-10-07

    申请号：US608605

    申请日：1996-02-29

    申请人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    发明人： Yuji Yokoyama ,  Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yutaka Kobayashi ,  Tatsumi Yamauchi ,  Shigeru Takahashi ,  Nobuyuki Gotou ,  Akira Ide

    IPC分类号： G11C7/10 ,  G11C8/10 ,  H03K19/0948 ,  G11C8/00

    CPC分类号： H03K19/0948 ,  G11C7/1051 ,  G11C7/1078 ,  G11C8/10

    摘要： An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.

    摘要翻译： 提供了对于使用例如公共NMOS来接收多个逻辑解码器门的一个输入的半导体存储器电路中的解码器特别有效的装置，其包括多个逻辑门，每个逻辑门具有用于分别接收第一输入的第一输入端 信号，并且每个都耦合到公共节点。 在一个实施例中，第一和第二开关元件也耦合到公共节点。 第一和第二开关元件都耦合到第二输入端子，用于接收多个逻辑门公共的第二输入信号，并且它们都响应于第二输入信号互相互补。 还提供了一种用于这种半导体存储器电路的改进的读/写布置，该电路包括用于在写入操作期间公共读取线与数据线的连接的电路。 这通过在写入期间去除公共读取线的负载来增强写入速度。

    Semiconductor memory having transistors which drive data lines in accordance with values of write data and column select signal
    8.
    发明授权
    Semiconductor memory having transistors which drive data lines in accordance with values of write data and column select signal 失效
    具有根据写数据和列选择信号的值驱动数据线的晶体管的半导体存储器

    公开(公告)号：US5285414A

    公开(公告)日：1994-02-08

    申请号：US765838

    申请日：1991-09-26

    申请人： Tatsumi Yamauchi ,  Masahiro Iwamura ,  Kazutaka Mori

    发明人： Tatsumi Yamauchi ,  Masahiro Iwamura ,  Kazutaka Mori

    IPC分类号： G11C7/12 ,  G11C11/419 ,  G11C11/40

    CPC分类号： G11C7/12 ,  G11C11/419

    摘要： A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states. Besides, in the case where the write enable signal designates the write operation, each of them operates in accordance with the value of the input data, to fall into ON state and draw the corresponding data line to the low level in the case of driving the data lines to the low level.

    摘要翻译： 半导体存储器包括写驱动器，其被提供以对应于相应的数据线，并且通过字线的控制与存储器单元连接的数据线在写入操作中被驱动。 写驱动器包括第一组的MOSFET和第二组的MOSFET。 在写入使能信号不表示写入操作的情况下，第一组的MOSFET通常处于ON状态以上拉数据线。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作，以在将数据线驱动到“ 高“电平并且在将数据线驱动到”低“电平的情况下落入OFF状态。 另一方面，第二组的MOSFET通常处于OFF状态。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作以进入ON状态，并且在驱动该操作的情况下将相应的数据线绘制到低电平 数据线到低电平。

    Semiconductor memory
    9.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US5657264A

    公开(公告)日：1997-08-12

    申请号：US159256

    申请日：1993-11-30

    申请人： Tatsumi Yamauchi ,  Masahiro Iwamura ,  Kazutaka Mori

    发明人： Tatsumi Yamauchi ,  Masahiro Iwamura ,  Kazutaka Mori

    IPC分类号： G11C7/12 ,  G11C11/419 ,  G11C7/00

    CPC分类号： G11C7/12 ,  G11C11/419

    摘要： A semiconductor memory comprises a write driver which is provided to correspond to respective data line and by which data lines connected with a memory cell through the control of a word line are driven in a write operation. The write driver includes MOSFETs of first group and MOSFETs of second group. In a case where a write enable signal does not designate the write operation, the MOSFETs of the first group are normally in ON states to pull up the data lines. Besides, in a case where the write enable signal designates the write operation, each of them operates in accordance with the value of input data, to maintain the ON states and pull up the corresponding data line in case of driving the data line to a "high" level and to fall into OFF states in case of driving the data line to a "low" level. On the other hand, the MOSFETs of the second group are normally in OFF states. Besides, in the case where the write enable signal designates the write operation, each of them operates in accordance with the value of the input data, to fall into ON state and draw the corresponding data line to the low level in the case of driving the data lines to the low level.

    摘要翻译： 半导体存储器包括写驱动器，其被提供以对应于相应的数据线，并且通过字线的控制与存储器单元连接的数据线在写入操作中被驱动。 写驱动器包括第一组的MOSFET和第二组的MOSFET。 在写入使能信号不表示写入操作的情况下，第一组的MOSFET通常处于ON状态以上拉数据线。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作，以在将数据线驱动到“ 高“电平并且在将数据线驱动到”低“电平的情况下落入OFF状态。 另一方面，第二组的MOSFET通常处于OFF状态。 此外，在写入使能信号指定写入操作的情况下，它们中的每一个根据输入数据的值进行操作以进入ON状态，并且在驱动该操作的情况下将相应的数据线绘制到低电平 数据线到低电平。