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    Memory device
    2.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US06337833B1

    公开(公告)日：2002-01-08

    申请号：US09346919

    申请日：1999-07-02

    申请人： Kazuyuki Kanazashi ,  Toshiya Uchida ,  Masaki Okuda

    发明人： Kazuyuki Kanazashi ,  Toshiya Uchida ,  Masaki Okuda

    IPC分类号： G11C800

    CPC分类号： G11C7/225 ,  G11C7/1051 ,  G11C7/1072

    摘要： One aspect of the present invention is that, when the memory is in the non-power-down state, the supply of clock signals to the data output circuit is limited to the read status after the reception of a read command, and no clock signal supply is performed when either the active status or the write status is in effect. In the best aspect, furthermore, in the read status after the reception of a read command, the supply of clock signals to the data output circuit starts after a number of clock signals corresponding to a set CAS latency following the read command, and stops after a number of clock signals corresponding to a set burst length, after the output of the read out data from the data output circuit starts. Accordingly, even in the non-power-down state, clock signals are only supplied during the time required for the read out data to be actually output from the data output circuit to the outside, whereby it is possible to reduce the number of clock signal supply actions that require large current drive.

    摘要翻译： 本发明的一个方面是，当存储器处于非掉电状态时，向数据输出电路提供时钟信号被限制在接收到读命令之后的读状态，并且没有时钟信号 当活动状态或写入状态都有效时执行供电。 此外，在最佳方面，在接收到读取命令之后的读取状态下，在与读取命令之后的设定的CAS延迟相对应的多个时钟信号之后，向数据输出电路提供时钟信号开始，并且在后面停止 在从数据输出电路输出读出数据开始之后，与设定的突发长度对应的多个时钟信号。 因此，即使在非掉电状态下，时钟信号仅在从数据输出电路向外部输出的读出数据所需的时间内提供，从而可以减少时钟信号的数量 提供需要大电流驱动的动作。

    Semiconductor memory device having error correction function for data reading during refresh operation
    4.
    发明授权
    Semiconductor memory device having error correction function for data reading during refresh operation 有权
    具有用于刷新操作期间的数据读取的纠错功能的半导体存储器件

    公开(公告)号：US06535452B2

    公开(公告)日：2003-03-18

    申请号：US10097621

    申请日：2002-03-15

    申请人： Masaki Okuda ,  Toshiya Uchida

    发明人： Masaki Okuda ,  Toshiya Uchida

    IPC分类号： G11C800

    CPC分类号： G06F11/1032 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/065 ,  G11C2207/108

    摘要： A semiconductor memory device includes a plurality of memory blocks, each of which is refreshed independently of one another, m (m>1) data pins, each of which continuously receives or outputs n (n>1) data pieces, a conversion circuit which converts data of each of the data pins between parallel data and serial data, m×n data bus lines on which the n data pieces are expanded in parallel with respect to each of the m data pins, m address selection lines which are connected to m respective blocks of the memory blocks corresponding to the m respective data pins, and are simultaneously activated, the activation of any one of the address selection lines connecting the data bus lines to a corresponding one of the m respective blocks and resulting in the n data pieces being input/output to/from the corresponding one of the m respective blocks.

    摘要翻译： 一种半导体存储器件包括多个存储块，每个存储块彼此独立地刷新，m（m> 1）个数据引脚，每个存储块连续地接收或输出n（n> 1）个数据段，转换电路 在并行数据和串行数据之间转换每个数据引脚的数据，相对于每个m个数据引脚并行扩展n个数据段的m×n数据总线，连接到m个相应块的m个地址选择线 的对应于各个数据引脚的存储器块，并且同时被激活，将数据总线线路中的任何一个地址选择线激活到相应的m个块中的相应一个，并且导致n个数据段被输入 /输出到相应的m个相应块中的一个。

    Memory device
    5.
    发明授权
    Memory device 有权
    内存设备

    公开(公告)号：US6104659A

    公开(公告)日：2000-08-15

    申请号：US338599

    申请日：1999-06-23

    申请人： Yoshimasa Yagishita ,  Toshiya Uchida ,  Masaki Okuda

    发明人： Yoshimasa Yagishita ,  Toshiya Uchida ,  Masaki Okuda

    IPC分类号： G11C11/413 ,  G05F1/00 ,  G11C5/14 ,  G11C11/401 ,  G11C11/406 ,  G11C11/407 ,  G11C7/00

    CPC分类号： G11C5/143 ,  G11C5/147

    摘要： A memory device comprises: a plurality of banks each of which includes an array of memory cells; and at least a first and a second internal power generator, provided for each of the plurality of banks, for generating an internal power source voltage which differs from a voltage supplied by an external power source. If the internal common power source voltage in the memory device is lower than the first voltage when the power is on, the first and the second internal power generators in a plurality of banks are activated so as to rapidly raise the common internal power source voltage. When the common internal power source voltage in the memory device is higher than the first voltage and lower than the second voltage, the second internal power generators in the banks are activated to compensate for a drop in the internal power source voltage, which is caused by current leakage. When the internal power source voltage in a bank in the activated state is lower than the third voltage, the first and the second internal power generators in the corresponding bank are activated and satisfactorily drive the internal power source voltage in the bank so as to operate the memory device at a high speed.

    摘要翻译： 存储器件包括：多个存储体，每个存储体包括存储器单元的阵列; 以及为多个组中的每一个提供的至少第一和第二内部发电机，用于产生不同于由外部电源提供的电压的内部电源电压。 如果在电源接通时存储器件内部的公共电源电压低于第一电压，则多个组中的第一和第二内部发电机被激活，以便迅速提高公共内部电源电压。 当存储器件中的公共内部电源电压高于第一电压并低于第二电压时，该组中的第二内部发电机被激活以补偿内部电源电压的下降，这是由 电流泄漏。 当处于激活状态的组中的内部电源电压低于第三电压时，相应组中的第一和第二内部发电机被激活并令人满意地驱动组中的内部电源电压，以便操作 高速存储设备。

    GRID COMPUTING SYSTEM, MANAGEMENT APPARATUS, AND METHOD FOR MANAGING A PLURALITY OF NODES
    6.
    发明申请
    GRID COMPUTING SYSTEM, MANAGEMENT APPARATUS, AND METHOD FOR MANAGING A PLURALITY OF NODES 审中-公开
    网格计算系统，管理装置和管理多重节点的方法

    公开(公告)号：US20100205306A1

    公开(公告)日：2010-08-12

    申请号：US12702857

    申请日：2010-02-09

    申请人： Hiroshi Kayanuma ,  Kouitirou Takahasi ,  Masaki Okuda

    发明人： Hiroshi Kayanuma ,  Kouitirou Takahasi ,  Masaki Okuda

    IPC分类号： G06F15/16 ,  G06F9/46 ,  G06F15/173

    CPC分类号： G06F9/505 ,  G06F9/5094 ,  G06F2209/5019 ,  Y02D10/22

    摘要： A grid computing system includes a plurality of nodes for processing a plurality of jobs, and a management apparatus for managing the plurality of the nodes. Each of the nodes is switchable between a standby and an active status, respectively. And the management apparatus including, a job request unit for allotting a plurality of requests of jobs to any of the nodes in an active state, a prediction unit for predicting the number of the nodes in the active state optimal for predicted amount of jobs requested from the exterior at a future time when a predetermined time period lapses from the present time, and a controller for controlling switching of the nodes between the standby and active so as to control the predicted number of the nodes to start switching before the future time.

    摘要翻译： 网格计算系统包括用于处理多个作业的多个节点，以及用于管理多个节点的管理装置。 每个节点分别在待机状态和活动状态之间切换。 并且，所述管理装置包括：作业请求单元，用于将多个作业请求分配给处于活动状态的任何节点;预测单元，用于预测所述活动状态中的节点数目， 在从当前时间经过预定时间段的未来时间的外部，以及控制器，用于控制备用和活动之间的节点的切换，以便控制节点的预测数量在未来时间之前开始切换。

    Semiconductor integrated circuit for voltage detection
    7.
    发明申请
    Semiconductor integrated circuit for voltage detection 失效
    用于电压检测的半导体集成电路

    公开(公告)号：US20080246540A1

    公开(公告)日：2008-10-09

    申请号：US11878748

    申请日：2007-07-26

    申请人： Masaki Okuda

    发明人： Masaki Okuda

    IPC分类号： H01L25/00

    CPC分类号： H01L27/0682

    摘要： A semiconductor integrated circuit includes a semiconductor substrate, one or more wells formed in the semiconductor substrate, one or more diffusion layers formed in the one or more wells, a plurality of interconnects formed in an interconnect layer, the one or more diffusion layers and the plurality of interconnects being connected in series to provide a coupling between a first potential and a second potential, and a comparison circuit coupled to one of the interconnects set at a third potential between the first potential and the second potential, and configured to compare the third potential with a reference potential, wherein a first interconnect of the plurality of interconnects that is set to the first potential is connected to at least a first well of the one or more wells and connected to a first diffusion layer of the one or more diffusion layers that is formed in the first well.

    摘要翻译： 半导体集成电路包括半导体衬底，形成在半导体衬底中的一个或多个阱，形成在一个或多个阱中的一个或多个扩散层，形成在互连层中的多个互连，一个或多个扩散层和 多个互连串联连接以提供第一电位和第二电位之间的耦合，以及比较电路，其耦合到设置在第一电位和第二电位之间的第三电位的互连中的一个，并且被配置为将第三电位 具有参考电位的电位，其中被设置为第一电位的多个互连的第一互连连接到所述一个或多个阱的至少第一阱并连接到所述一个或多个扩散层的第一扩散层 这是在第一口井中形成的。

    Semiconductor memory, test method of semiconductor memory and system
    9.
    发明授权
    Semiconductor memory, test method of semiconductor memory and system 失效
    半导体存储器，半导体存储器和系统的测试方法

    公开(公告)号：US07675773B2

    公开(公告)日：2010-03-09

    申请号：US12130480

    申请日：2008-05-30

    申请人： Kaoru Mori ,  Toshikazu Nakamura ,  Jun Ohno ,  Masaki Okuda

    发明人： Kaoru Mori ,  Toshikazu Nakamura ,  Jun Ohno ,  Masaki Okuda

    IPC分类号： G11C11/34

    CPC分类号： G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/48 ,  G11C2029/1802

    摘要： An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column address signal supplied to the second address terminal group and supplies the received row address signal and the received column address signal to the row decoder and the column decoder during a second operation mode. The number of semiconductor memories that are tested at once can be increased by executing an operation test of the semiconductor memories in the second operation mode. In addition, it becomes possible to test a semiconductor memory using test assets for other semiconductor memories. Consequently, the test efficiency can be improved, and the test cost can be reduced.

    摘要翻译： 地址开关电路接收提供给第一地址端子组的行地址信号和提供给第二地址端子组的列地址信号。 此外，地址开关电路接收提供给第二地址端子组的行地址信号，然后接收提供给第二地址端子组的列地址信号，并将接收到的行地址信号和接收的列地址信号提供给行解码器， 列解码器在第二操作模式期间。 可以通过在第二操作模式中执行半导体存储器的操作测试来增加一次测试的半导体存储器的数量。 此外，可以使用用于其他半导体存储器的测试资产来测试半导体存储器。 因此，可以提高测试效率，并且可以降低测试成本。

    Semiconductor device having a power supply capacitor
    10.
    发明授权
    Semiconductor device having a power supply capacitor 有权
    具有电源电容器的半导体装置

    公开(公告)号：US07427885B2

    公开(公告)日：2008-09-23

    申请号：US11020169

    申请日：2004-12-27

    申请人： Masaki Okuda

    发明人： Masaki Okuda

    IPC分类号： G06F1/04

    CPC分类号： G06F1/26 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In order to prevent a signal of a signal wiring from receiving a bad influence due to a power supply capacitor, provided is a semiconductor including a high reference potential terminal and a low reference potential terminal composing power supply voltage terminals; a first MOS capacitor in which a gate of a p-channel MOS field effect transistor is connected to the low reference potential terminal, and a source and a drain are connected to the high reference potential terminal; and a first signal wiring connected to the gate via a parasitic capacitor and a signal in the low reference potential is supplied at the time of starting the power supply.

    摘要翻译： 为了防止信号线的信号由于电源电容器而受到不良影响，提供了包括构成电源电压端子的高参考电位端子和低基准电位端子的半导体; 第一MOS电容器，其中p沟道MOS场效应晶体管的栅极连接到低参考电势端子，源极和漏极连接到高参考电位端子; 并且在开始供电时提供经由寄生电容器连接到栅极的第一信号线和低基准电位的信号。