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公开(公告)号：US06647529B2
公开(公告)日：2003-11-11
申请号：US09761195
申请日：2001-01-18
IPC分类号： H03M1300
CPC分类号： H03M13/1545 , H03M13/1515 , H03M13/158 , H03M13/2909
摘要： The present invention attempts to speed up operations by a chien's searching apparatus used in error correction, to thereby miniaturize it and save on its power dissipation. To this end, the apparatus includes a plurality of arithmetic units which share an error-position polynomial calculating unit and an error-numeral polynomial calculating unit as well as selectors and registers, to thereby perform calculation on a plurality of orders in the same cycle. Also, a divider unit is shared in use. If no error is found, the divider unit is stopped.
摘要翻译： 本发明试图通过用于纠错的chien的搜索装置来加速操作，从而使其小型化并节省其功率消耗。 为此，该装置包括共享错误位置多项式计算单元和错误数字多项式计算单元以及选择器和寄存器的多个运算单元，从而对同一周期中的多个订单执行计算。 另外，在使用中共享一个分频器单元。 如果没有发现错误，则分频单元停止。
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公开(公告)号：US20110012245A1
公开(公告)日：2011-01-20
申请号：US12892165
申请日：2010-09-28
IPC分类号： H01L23/528
CPC分类号： H01L24/06 , H01L23/50 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06153 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48599 , H01L2224/49113 , H01L2224/4917 , H01L2224/49171 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/01058 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/3011 , H01L2224/78 , H01L2924/00
摘要： There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions. In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is different from an arrangement order of the function terminals on the external package.
摘要翻译： 提供了一种半导体器件，其采用连接到LSI上的外部封装的焊盘的布局，其中焊盘布置移位的之字形焊盘布局，这可以避免导线短路的发生，芯片的增加 由于避免短路，由于IO单元间隔的减少而导致的电源传播或GND噪声，以及由于焊盘位置的位移引起的信号传输延迟差异。 在半导体装置中，与外部封装上的功能端子连接的半导体元件上的多个焊盘沿着半导体元件的周边配置成两列，半导体元件上的多个焊盘的配置顺序与布置 外部封装上功能端子的顺序。
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公开(公告)号：US20060258135A1
公开(公告)日：2006-11-16
申请号：US10565006
申请日：2004-08-31
CPC分类号： H01L22/32 , G01R31/2831 , G01R31/2856 , G01R31/2884 , H01L27/0203 , H01L27/118 , H01L2224/05554
摘要： Each of plural semiconductor integrated circuits existing on a semiconductor wafer is provided with a function circuit (3), plural pads (4), and wirings (8) which are electrically connected to the pads (4) and contact bumps of a probe card (7), wherein at least two wirings (8a) and (8b) simultaneously contact one bump (6) in an area other than a bump area, without being in touch with each other, whereby wafer level burn-in is executed. Thereby, even when the chip area is reduced, wafer level burn-in can be carried out.
摘要翻译： 存在于半导体晶片上的多个半导体集成电路中的每一个设置有功能电路（3），电连接到焊盘（4）的多个焊盘（4）和布线（8）以及探针卡的接触凸块 7），其中至少两个布线（8a）和（8b）同时接触除了凸起区域之外的区域中的一个凸起（6），而不彼此接触，由此执行晶片级老化。 因此，即使当芯片面积减小时，也可以进行晶片级老化。
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公开(公告)号：US08035188B2
公开(公告)日：2011-10-11
申请号：US11658738
申请日：2005-05-30
申请人： Hiroaki Segawa , Masanori Hirofuji
发明人： Hiroaki Segawa , Masanori Hirofuji
IPC分类号： H01L21/70
CPC分类号： H01L24/06 , H01L22/32 , H01L27/0207 , H01L27/0251 , H01L2224/05553 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082 , H01L2924/14 , H01L2924/19043
摘要： Plural I/O cells (14) having electrode pads for wire bonding (13) are disposed with spaces (55) between them in the vicinity of a corner of an I/O region (11) of a semiconductor substrate (10), and power supply separation cells (16) not to be wire bonded, on which ESD (electrostatic discharge) protection circuits (4) having ESD protection transistors are amounted, are disposed between the respective I/O cells (14), whereby the chip size is reduced upon consideration of layout of the electrode pads.
摘要翻译： 具有用于引线接合的电极焊盘（13）的多个I / O单元（14）在它们之间在半导体衬底（10）的I / O区域（11）的拐角附近设置有空间（55），以及 在相应的I / O单元（14）之间设置在其上形成有ESD保护晶体管的ESD（静电放电）保护电路（4）的未被引线接合的电源分离单元（16），由此芯片尺寸 考虑到电极焊盘的布局而减小。
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公开(公告)号：US20090001364A1
公开(公告)日：2009-01-01
申请号：US11658738
申请日：2005-05-30
申请人： Hiroaki Segawa , Masanori Hirofuji
发明人： Hiroaki Segawa , Masanori Hirofuji
IPC分类号： H01L23/49
CPC分类号： H01L24/06 , H01L22/32 , H01L27/0207 , H01L27/0251 , H01L2224/05553 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082 , H01L2924/14 , H01L2924/19043
摘要： Plural I/O cells (14) having electrode pads for wire bonding (13) are disposed with spaces (55) between them in the vicinity of a corner of an I/O region (11) of a semiconductor substrate (10), and power supply separation cells (16) not to be wire bonded, on which ESD (electrostatic discharge) protection circuits (4) having ESD protection transistors are amounted, are disposed between the respective I/O cells (14), whereby the chip size is reduced upon consideration of layout of the electrode pads.
摘要翻译： 具有用于引线接合的电极焊盘（13）的多个I / O单元（14）在它们之间在半导体衬底（10）的I / O区域（11）的拐角附近设置有空间（55），以及 在相应的I / O单元（14）之间设置在其上形成有ESD保护晶体管的ESD（静电放电）保护电路（4）的未被引线接合的电源分离单元（16），由此芯片尺寸 考虑到电极焊盘的布局而减小。
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公开(公告)号：US08773825B2
公开(公告)日：2014-07-08
申请号：US13550318
申请日：2012-07-16
IPC分类号： H02H9/00
CPC分类号： H02H9/046 , H01L27/0248 , H01L27/0266
摘要： An electrode pad is provided above a circuit block of a semiconductor integrated circuit device. A junction point A and a junction point B are provided on connection lines connecting electrode pads to an internal circuit and an electrostatic discharge (ESD) protection circuit. The junction point A and the junction point B are positioned at locations closer to the ESD protection circuit than to the electrode pads.
摘要翻译： 电极焊盘设置在半导体集成电路器件的电路块的上方。 在将电极焊盘连接到内部电路和静电放电（ESD）保护电路的连接线上设有接合点A和接合点B. 接合点A和接合点B位于靠近ESD保护电路的位置，而不是电极焊盘。
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公开(公告)号：US07829983B2
公开(公告)日：2010-11-09
申请号：US11997700
申请日：2006-07-28
IPC分类号： H01L23/495
CPC分类号： H01L24/06 , H01L23/50 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06153 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48599 , H01L2224/49113 , H01L2224/4917 , H01L2224/49171 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/01058 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/3011 , H01L2224/78 , H01L2924/00
摘要： There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions. In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is different from an arrangement order of the function terminals on the external package.
摘要翻译： 提供了一种半导体器件，其采用连接到LSI上的外部封装的焊盘的布局，其中焊盘布置移位的之字形焊盘布局，这可以避免导线短路的发生，芯片的增加 由于避免短路，由于IO单元间隔的减少而导致的电源传播或GND噪声，以及由于焊盘位置的位移引起的信号传输延迟差异。 在半导体装置中，与外部封装上的功能端子连接的半导体元件上的多个焊盘沿着半导体元件的周边配置成两列，半导体元件上的多个焊盘的配置顺序与布置 外部封装上功能端子的顺序。
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公开(公告)号：US20090146273A1
公开(公告)日：2009-06-11
申请号：US11997700
申请日：2006-07-28
IPC分类号： H01L23/495
CPC分类号： H01L24/06 , H01L23/50 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/85 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/06153 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48599 , H01L2224/49113 , H01L2224/4917 , H01L2224/49171 , H01L2224/49431 , H01L2224/85399 , H01L2924/00014 , H01L2924/01033 , H01L2924/01058 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/3011 , H01L2224/78 , H01L2924/00
摘要： There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions.In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is made different from an arrangement order of the function terminals on the external package.
摘要翻译： 提供了一种半导体器件，其采用连接到LSI上的外部封装的焊盘的布局，其中焊盘布置移位的之字形焊盘布局，这可以避免导线短路的发生，芯片的增加 由于避免短路，由于IO单元间隔的减少而导致的电源传播或GND噪声，以及由于焊盘位置的位移引起的信号传输延迟差异。 在半导体装置中，与外部封装上的功能端子连接的半导体元件上的多个焊盘沿着半导体元件的周边配置成两列，半导体元件上的多个焊盘的排列顺序与 功能端子在外部封装上的布置顺序。
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公开(公告)号：US20070205794A1
公开(公告)日：2007-09-06
申请号：US11639278
申请日：2006-12-15
申请人： Shusaku Ota , Hiroaki Segawa , Masanori Hirofuji
发明人： Shusaku Ota , Hiroaki Segawa , Masanori Hirofuji
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , H01L24/06 , H01L2224/05554 , H01L2224/0603 , H01L2924/14 , H01L2924/00
摘要： A power supply potential and a ground potential are supplied to a test-use power supply pad and a test-use ground pad, respectively. The power supply potential supplied to the test-use power supply pad is transferred to power supply lines and then to each circuit block via a test-use power supply line and a potential transfer circuit including a diode device. A voltage drop is caused by each of the diode devices. To cope with the voltage drop, however, respective sizes of the diode devices and resistance components of the potential transfer circuits are configured so that a uniform voltage drop is generated at each of the power supply lines.
摘要翻译： 电源电位和接地电位分别提供给测试用电源焊盘和测试用接地焊盘。 提供给测试用电源焊盘的电源电位通过测试用电源线和包括二极管器件的电位传输电路传送到电源线，然后传送到每个电路块。 每个二极管器件引起电压降。 然而，为了应对电压降，二极管器件的各个尺寸和电位传输电路的电阻分量被配置成使得在每个电源线处产生均匀的电压降。
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公开(公告)号：US07256604B1
公开(公告)日：2007-08-14
申请号：US11639278
申请日：2006-12-15
申请人： Shusaku Ota , Hiroaki Segawa , Masanori Hirofuji
发明人： Shusaku Ota , Hiroaki Segawa , Masanori Hirofuji
IPC分类号： G01R31/26
CPC分类号： G01R31/2879 , H01L24/06 , H01L2224/05554 , H01L2224/0603 , H01L2924/14 , H01L2924/00
摘要： A power supply potential and a ground potential are supplied to a test-use power supply pad and a test-use ground pad, respectively. The power supply potential supplied to the test-use power supply pad is transferred to power supply lines and then to each circuit block via a test-use power supply line and a potential transfer circuit including a diode device. A voltage drop is caused by each of the diode devices. To cope with the voltage drop, however, respective sizes of the diode devices and resistance components of the potential transfer circuits are configured so that a uniform voltage drop is generated at each of the power supply lines.
摘要翻译： 电源电位和接地电位分别提供给测试用电源焊盘和测试用接地焊盘。 提供给测试用电源焊盘的电源电位通过测试用电源线和包括二极管器件的电位传输电路传送到电源线，然后传送到每个电路块。 每个二极管器件引起电压降。 然而，为了应对电压降，二极管器件的各个尺寸和电位传输电路的电阻分量被配置成使得在每个电源线处产生均匀的电压降。
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