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40 条记录 (耗时 0.024 秒)

    Suck back valve
    1.
    发明授权
    Suck back valve 失效
    吸回阀

    公开(公告)号：US5950924A

    公开(公告)日：1999-09-14

    申请号：US106345

    申请日：1998-06-29

    申请人： Masatoshi Hatakeyama ,  Kenichi Kurosawa

    发明人： Masatoshi Hatakeyama ,  Kenichi Kurosawa

    IPC分类号： B05C11/10 ,  F16K23/00 ,  B05B15/00

    CPC分类号： F16K23/00

    摘要： A suck back valve is equipped with a displacement speed regulating device made up of an ER (Electro-rheological) fluid filled in a chamber and whose viscosity changes in correspondence with the size of an external electric field, a coil member which generates the external electric field in response to an applied voltage, and a constriction which regulates a flow amount of the ER fluid between an upper-side chamber and a lower-side chamber of the chamber.

    摘要翻译： 吸回阀配备有位移调速装置，其由填充在室内的ER（电流变性）流体构成，其粘度随外部电场的大小而变化，产生外部电力的线圈构件 响应于施加电压的场，以及调节在室的上侧室和下侧室之间的ER流体的流量的收缩部。

    Input/output device for connection and disconnection of active lines
    3.
    发明授权
    Input/output device for connection and disconnection of active lines 有权
    用于连接和断开有源线路的输入/输出设备

    公开(公告)号：US06393509B2

    公开(公告)日：2002-05-21

    申请号：US09932973

    申请日：2001-08-21

    申请人： Tsutomu Yamada ,  Kenichi Kurosawa ,  Yasuo Kaminaga ,  Kouji Masui ,  Akihiro Ohashi

    发明人： Tsutomu Yamada ,  Kenichi Kurosawa ,  Yasuo Kaminaga ,  Kouji Masui ,  Akihiro Ohashi

    IPC分类号： G06F1300

    CPC分类号： G06F13/4081 ,  G06F1/189 ,  Y02D10/14 ,  Y02D10/151

    摘要： There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal. An expansion device 800 comprises an electronic circuit 400 and a MOS switch 300, and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state, inside the expansion device the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260. At the time of insertion or removal, adverse influence is not exerted on the signal transmission on the system bus, and effects of load variation on the main power supply are reduced.

    摘要翻译： 提供了一种输入/输出装置，其在插入或移除时对连接到系统总线的其它扩展装置没有任何不利影响。扩展装置800包括电子电路400和MOS开关300，并且被连接 通过具有长和短引脚的连接器连接到系统总线（BUS）。 膨胀装置800是两个电源系统，即稳定的电源250和不稳定的电源260.在插入或移除扩展装置800时，向MOS开关300提供电力和高阻抗保持电路 通过一对长引脚稳定供电，为了可靠地将MOS开关300置于高阻抗状态，高阻抗保持电路350在扩展装置的内部驱动开/关控制端子，并且向 来自不稳定电源260的电子电路400.在插入或移除时，不会对系统总线上的信号传输产生不利影响，并且降低对主电源的负载变化的影响。

    Uninterruptible clock supply apparatus for fault tolerant computer system
    4.
    发明授权
    Uninterruptible clock supply apparatus for fault tolerant computer system 失效
    用于容错计算机系统的不间断时钟提供装置

    公开(公告)号：US5852728A

    公开(公告)日：1998-12-22

    申请号：US585344

    申请日：1996-01-11

    申请人： Koji Matsuda ,  Soichi Takaya ,  Yoshihiro Miyazaki ,  Kenichi Kurosawa ,  Shinichiro Yamaguchi ,  Sako Ishikawa ,  Akira Yamagiwa ,  Masao Inoue ,  Kenji Kashiwagi

    发明人： Koji Matsuda ,  Soichi Takaya ,  Yoshihiro Miyazaki ,  Kenichi Kurosawa ,  Shinichiro Yamaguchi ,  Sako Ishikawa ,  Akira Yamagiwa ,  Masao Inoue ,  Kenji Kashiwagi

    IPC分类号： G06F1/04 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G06F1/06

    CPC分类号： G06F11/1604 ,  G06F1/04 ,  G06F11/1679 ,  G06F11/20

    摘要： The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the plural processing units comprises a clock source, a clock selector, a clock stop detection unit, a clock phase adjusting unit, and a phase coincidence detection/operation suppression/resetting unit, whereby when switching over from a faulty clock source to a normal clock source in the event of clock failure, the clock phase adjusting unit ensures continuity in the output clock signals. The clock phase adjusting unit provided in the subsequent stage of the clock selector inserts the PLL circuit having an overdamping response characteristic obtained by lowering the gain of its loop filter.

    摘要翻译： 本发明涉及双时钟源中的任何一个时钟源的时钟源切换，而不会影响双系统中的时钟输出，从而防止其中的处理器的故障。 在本发明的容错计算机系统中，多个处理单元中的每一个包括时钟源，时钟选择器，时钟停止检测单元，时钟相位调整单元和相位一致检测/操作抑制/复位单元，由此 在时钟故障的情况下，当从故障时钟源切换到正常时钟源时，时钟相位调整单元确保输出时钟信号的连续性。 设置在时钟选择器的后续级中的时钟相位调整单元插入具有通过降低其环路滤波器的增益而获得的过阻抗响应特性的PLL电路。

    Parallel processing apparatus and method capable of switching parallel and successive processing modes
    5.
    发明授权
    Parallel processing apparatus and method capable of switching parallel and successive processing modes 失效
    并行处理装置和方法能够切换并行和连续的处理模式

    公开(公告)号：US5287465A

    公开(公告)日：1994-02-15

    申请号：US549916

    申请日：1990-07-09

    申请人： Kenichi Kurosawa ,  Shigeya Tanaka ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh

    发明人： Kenichi Kurosawa ,  Shigeya Tanaka ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh

    IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/177 ,  G06F9/00

    CPC分类号： G06F9/30189 ,  G06F9/30181 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

    摘要： When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed. Further, the parallel processing apparatus making great account of compatibility of a great part of software reads out m instructions without using the processing state flag, decodes the m instructions, checks whether a branch instruction exists in the k-th instruction, then executes the first to the (k+1)-th instructions in k+1 arithmetic units, and prevent execution of the (k+ 2)-th to m-th instructions. By executing the k-th branch instruction, the parallel processing apparatus calculates an address nm+h of its branch destination, performs calculation to check whether the condition is satisfied or not, then prevents execution of instructions of addresses nm to nm+h-1, and executes instructions of addresses nm+h to (n+1)m. In this way, the parallel processing apparatus executes a plurality of instructions and successively executes branch instructions.

    摘要翻译： 当执行常规软件的连续处理时，并行处理装置将处理状态判别标志关闭，一次将程序数增加1，读出一个指令，并在运算单元中处理该指令。 当执行新软件的并行处理时，并行处理装置将处理状态判别转为一次，一次增加程序数m，读出m个指令，并对m个运算单元中的m个指令进行并行处理。 为了选择上述两种处理之一，添加具有改变处理状态判别标志的功能的识别切换指令。 指令根据处理状态判别标志在算术单元中进行处理。 以这种方式，连续处理和并行处理具有兼容性并且被选择性地执行。 此外，大量软件的兼容性的并行处理装置在不使用处理状态标志的情况下读出m个指令，对m个指令进行解码，检查第k个指令中是否存在转移指令，然后执行第一 到第k + 1个算术单元中的第（k + 1）个指令，并且防止执行第（k + 2）至第m指令。 通过执行第k个分支指令，并行处理装置计算其分支目的地的地址nm + h，执行计算以检查条件是否满足，然后防止执行地址nm到nm + h-1的指令 并且执行地址nm + h至（n + 1）m的指令。 以这种方式，并行处理装置执行多个指令，并连续执行分支指令。

    Optical communication method, optical linking device and optical communication system
    8.
    发明授权
    Optical communication method, optical linking device and optical communication system 失效
    光通信方法，光连接装置和光通信系统

    公开(公告)号：US07558483B2

    公开(公告)日：2009-07-07

    申请号：US10897074

    申请日：2004-07-23

    申请人： Hiroshi Arita ,  Tetsuaki Nakamikawa ,  Kenichi Kurosawa ,  Hiroaki Fukumaru ,  Hisao Ogawa

    发明人： Hiroshi Arita ,  Tetsuaki Nakamikawa ,  Kenichi Kurosawa ,  Hiroaki Fukumaru ,  Hisao Ogawa

    IPC分类号： H04B10/00

    CPC分类号： H04B10/271 ,  G06F13/4022 ,  H04B10/27 ,  H04B10/278

    摘要： The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.

    摘要翻译： 该系统包括用于在所述电气总线未被驱动（OFF模式）下观察所述电动总线的模式和所述光纤的模式的光学总线桥接装置，使得通过光纤连接的两条电动总线的模式为 使总线同时由多个节点驱动。 虽然所述电气总线中的一个或两个已经被连接到其上的节点驱动（ON模式），但是已经从被驱动到所述光纤的总线连续地产生光输出，并且在从所述光纤输入光 没有观察到所述总线的模式，而是向输入光的一侧的电力总线产生电力输出以驱动总线。 光总线桥接装置在光总线桥接装置向光纤输出信号之后光纤在预定时间内不变化时，改变电气总线的模式。