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公开(公告)号：US20120161321A1
公开(公告)日：2012-06-28
申请号：US12978359
申请日：2010-12-23
IPC分类号： H01L23/482 , H01L21/3205 , H01L21/283 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/41791 , H01L21/283 , H01L21/3205 , H01L23/482 , H01L23/485 , H01L29/0895 , H01L29/456 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulting layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.
摘要翻译： 公开了用于在硅半导体器件中形成接触的技术。 在一些实施例中，过渡层与硅半导体接触表面形成非反应性界面。 在一些这种情况下，导电材料提供触点和与硅表面形成非反应性界面的材料。 在其他情况下，薄的半导体或绝缘层提供与硅表面的非反应性界面并且耦合到触点的导电材料。 这些技术可以例如在平面或非平面（例如，双栅极和三栅极FinFET））晶体管器件中实现。
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公开(公告)号：US09166004B2
公开(公告)日：2015-10-20
申请号：US12978359
申请日：2010-12-23
IPC分类号： H01L29/78 , H01L21/02 , H01L23/48 , H01L23/52 , H01L29/40 , H01L21/3205 , H01L21/4763 , H01L21/44 , H01L29/08 , H01L23/485 , H01L29/45 , H01L23/482 , H01L21/283
CPC分类号： H01L29/41791 , H01L21/283 , H01L21/3205 , H01L23/482 , H01L23/485 , H01L29/0895 , H01L29/456 , H01L29/7851 , H01L2924/0002 , H01L2924/00
摘要： Techniques are disclosed for forming contacts in silicon semiconductor devices. In some embodiments, a transition layer forms a non-reactive interface with the silicon semiconductor contact surface. In some such cases, a conductive material provides the contacts and the material forming a non-reactive interface with the silicon surface. In other cases, a thin semiconducting or insulating layer provides the non-reactive interface with the silicon surface and is coupled to conductive material of the contacts. The techniques can be embodied, for instance, in planar or non-planar (e.g., double-gate and tri-gate FinFETs) transistor devices.
摘要翻译： 公开了用于在硅半导体器件中形成接触的技术。 在一些实施例中，过渡层与硅半导体接触表面形成非反应性界面。 在一些这种情况下，导电材料提供触点和与硅表面形成非反应性界面的材料。 在其他情况下，薄的半导体或绝缘层提供与硅表面的非反应性界面并且耦合到触点的导电材料。 这些技术可以例如在平面或非平面（例如，双栅极和三栅极FinFET））晶体管器件中实现。
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公开(公告)号：US10483385B2
公开(公告)日：2019-11-19
申请号：US13995914
申请日：2011-12-23
申请人： Stephen M. Cea , Cory E. Weber , Patrick H. Keys , Seiyon Kim , Michael G. Haverty , Sadasivan Shankar
发明人： Stephen M. Cea , Cory E. Weber , Patrick H. Keys , Seiyon Kim , Michael G. Haverty , Sadasivan Shankar
IPC分类号： H01L29/775 , B82Y10/00 , H01L29/66 , H01L29/06 , H01L29/417 , H01L29/78 , H01L29/786 , B82Y40/00 , H01L29/16
摘要： Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.
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公开(公告)号：US20120153478A1
公开(公告)日：2012-06-21
申请号：US12973773
申请日：2010-12-20
CPC分类号： H01L23/53238 , H01L21/76843 , H01L21/76858 , H01L21/76873 , H01L21/76877 , H01L2924/0002 , H01L2924/00
摘要： Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.
摘要翻译： 提供了用于集成电路的电互连和制造互连的方法。 提供了包括铜互连件的装置，其具有包含银和第二成分（诸如镧，钛，钨，锆，锑或钙）的金属衬里层。 方法包括提供具有在其中形成的沟槽或通孔的衬底，在特征的表面上形成银合金层，其包含银和选自镧，钛，钨，锆，锑和钙的第二组分， 沉积铜种子层，并将铜沉积到特征中。
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公开(公告)号：US20140209855A1
公开(公告)日：2014-07-31
申请号：US13995914
申请日：2011-12-23
申请人： Stephen M. Cea , Cory E. Weber , Patrick H. Keys , Seiyon Kim , Michael G. Haverty , Sadasivan Shankar
发明人： Stephen M. Cea , Cory E. Weber , Patrick H. Keys , Seiyon Kim , Michael G. Haverty , Sadasivan Shankar
IPC分类号： H01L29/775 , H01L29/66
摘要： Nanowire structures having wrap-around contacts are described. For example, a nanowire semiconductor device includes a nanowire disposed above a substrate. A channel region is disposed in the nanowire. The channel region has a length and a perimeter orthogonal to the length. A gate electrode stack surrounds the entire perimeter of the channel region. A pair of source and drain regions is disposed in the nanowire, on either side of the channel region. Each of the source and drain regions has a perimeter orthogonal to the length of the channel region. A first contact completely surrounds the perimeter of the source region. A second contact completely surrounds the perimeter of the drain region.
摘要翻译： 描述具有环绕触点的纳米线结构。 例如，纳米线半导体器件包括设置在衬底之上的纳米线。 沟道区域设置在纳米线中。 通道区域具有与长度正交的长度和周长。 栅电极堆叠围绕通道区域的整个周边。 一对源极和漏极区域设置在沟道区域的任一侧上的纳米线中。 源极和漏极区域中的每一个具有与沟道区域的长度正交的周长。 第一接触件完全围绕源区域的周边。 第二触点完全围绕漏区的周边。
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公开(公告)号：US08779589B2
公开(公告)日：2014-07-15
申请号：US12973773
申请日：2010-12-20
IPC分类号： H01L23/52 , H01L21/48 , H01L21/768 , H01L23/532 , H01L21/44
CPC分类号： H01L23/53238 , H01L21/76843 , H01L21/76858 , H01L21/76873 , H01L21/76877 , H01L2924/0002 , H01L2924/00
摘要： Electrical interconnects for integrated circuits and methods of fabrication of interconnects are provided. Devices are provided comprising copper interconnects having metallic liner layers comprising silver and a second component, such as, lanthanum, titanium, tungsten, zirconium, antimony, or calcium. Methods include providing a substrate having a trench or via formed therein, forming a silver alloy layer, comprising silver and a second component selected from the group consisting of lanthanum, titanium, tungsten, zirconium, antimony, and calcium, onto surfaces of the feature, depositing a copper seed layer, and depositing copper into the feature.
摘要翻译： 提供了用于集成电路的电互连和制造互连的方法。 提供了包括铜互连件的装置，其具有包含银和第二成分（诸如镧，钛，钨，锆，锑或钙）的金属衬里层。 方法包括提供具有在其中形成的沟槽或通孔的衬底，在特征的表面上形成银合金层，其包含银和选自镧，钛，钨，锆，锑和钙的第二组分， 沉积铜种子层，并将铜沉积到特征中。
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7.发明授权公开(公告)号：US08633534B2
公开(公告)日：2014-01-21
申请号：US12976385
申请日：2010-12-22
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L29/785 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： An apparatus comprises a substrate, a phonon-decoupling layer formed on the substrate, a gate dielectric layer formed on the phonon-decoupling layer, a gate electrode formed on the gate dielectric layer, a pair of spacers formed on opposite sides of the gate electrode, a source region formed in the substrate subjacent to the phonon-decoupling layer, and a drain region formed in the substrate subjacent to the phonon-decoupling layer. The phonon-decoupling layer prevents the formation of a silicon dioxide interfacial layer and reduces coupling between high-k phonons and the field in the substrate.
摘要翻译： 一种装置，包括衬底，形成在衬底上的声子去耦层，形成在声子去耦层上的栅介质层，形成在栅介质层上的栅电极，形成在栅电极的相对侧上的一对隔离层 ，形成在与声子去耦层相邻的衬底中的源极区，以及形成在与声子去耦层相邻的衬底中的漏极区。 声子去耦层防止二氧化硅界面层的形成，并减少高k声子与衬底中的场之间的耦合。
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公开(公告)号：US20120161251A1
公开(公告)日：2012-06-28
申请号：US12976385
申请日：2010-12-22
IPC分类号： H01L29/78
CPC分类号： H01L29/785 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： An apparatus comprises a substrate, a phonon-decoupling layer formed on the substrate, a gate dielectric layer formed on the phonon-decoupling layer, a gate electrode formed on the gate dielectric layer, a pair of spacers formed on opposite sides of the gate electrode, a source region formed in the substrate subjacent to the phonon-decoupling layer, and a drain region formed in the substrate subjacent to the phonon-decoupling layer. The phonon-decoupling layer prevents the formation of a silicon dioxide interfacial layer and reduces coupling between high-k phonons and the field in the substrate.
摘要翻译： 一种装置，包括衬底，形成在衬底上的声子去耦层，形成在声子去耦层上的栅介质层，形成在栅介质层上的栅电极，形成在栅电极的相对侧上的一对隔离层 ，形成在与声子去耦层相邻的衬底中的源极区，以及形成在与声子去耦层相邻的衬底中的漏极区。 声子去耦层防止二氧化硅界面层的形成，并减少高k声子与衬底中的场之间的耦合。
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公开(公告)号：US20070269646A1
公开(公告)日：2007-11-22
申请号：US11437775
申请日：2006-05-18
CPC分类号： H01L21/02115 , C23C14/0605 , C23C14/5846 , C23C16/26 , C23C16/56 , C30B29/04 , C30B33/00 , H01L21/02203 , H01L21/3105 , H01L21/31105 , H01L21/3146 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L2221/1047 , Y10T428/249967 , Y10T428/30
摘要： A porous diamond dielectric material having a low dielectric constant and a method of forming such a material are described herein. A porous diamond dielectric material demonstrates high mechanical strength and has a low dielectric constant because of the presence of the pores. The dielectric constant is further decreased by the conversion of the sp2 type carbon bond terminations of the interior surface of the pores to sp3 type carbon bond terminations. This is accomplished by hydrogenation of the porous diamond dielectric material.
摘要翻译： 本文描述了具有低介电常数的多孔金刚石介电材料和形成这种材料的方法。 由于孔的存在，多孔金刚石介电材料表现出高机械强度并具有低介电常数。 通过将孔内表面的第二种类型的碳键端接转换成sp 3+型碳键终端，介电常数进一步降低。 这是通过多孔金刚石介电材料的氢化来实现的。
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公开(公告)号：US20050287787A1
公开(公告)日：2005-12-29
申请号：US10880632
申请日：2004-06-29
IPC分类号： H01L21/316 , H01L21/768 , H01L21/4763 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/02178 , H01L21/02203 , H01L21/02274 , H01L21/02362 , H01L21/31695 , H01L21/76807 , H01L21/7682 , H01L2221/1047
摘要： A method for selecting and forming a low-k, relatively high E porous ceramic film in a semiconductor device is described. A ceramic material is selected having a relatively high Young's modulus and relatively lower dielectric constant. The k is reduced by making the film porous.
摘要翻译： 描述了在半导体器件中选择和形成低k，较高E多孔陶瓷膜的方法。 选择具有相对高的杨氏模量和相对较低的介电常数的陶瓷材料。 通过使膜多孔化来减小k。
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