公开(公告)号：US5757079A

公开(公告)日：1998-05-26

申请号：US577677

申请日：1995-12-21

申请人： Michael McAllister ,  James McDonald ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Gordon J. Robbins ,  Madhavan Swaminathan ,  George Eugene White

发明人： Michael McAllister ,  James McDonald ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Gordon J. Robbins ,  Madhavan Swaminathan ,  George Eugene White

IPC分类号： H01L21/48 ,  H01L23/538 ,  H05K3/00 ,  H05K3/22 ,  H05K3/46 ,  H01L23/48 ,  H01L23/52 ,  H01L23/58 ,  H01L29/40

CPC分类号： H01L23/5382 ,  H01L21/485 ,  H05K3/225 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K2203/162 ,  H05K3/0082 ,  H05K3/4644

摘要： A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

摘要翻译： 提供了一种具有定义的修补线的多层薄膜结构和用于修复多层薄膜结构（MLTF）中的互连和/或制造工程电荷（EC）的方法。 该方法包括使用光刻技术（例如直接写入曝光技术）来确定在与结构的顶部金属层相邻的薄膜层处的MLTF中的任何互连缺陷，以限定修复互连所需的顶面连接和/或使EC ，并使用添加剂或阴极金属化技术形成顶表面金属化和修补线。

公开(公告)号：US5747095A

公开(公告)日：1998-05-05

申请号：US800945

申请日：1997-02-14

申请人： Michael McAllister ,  Eric Daniel Perfecto ,  James McDonald ,  Keshav Prasad ,  Gordon J. Robbins ,  Chandrika Prasad ,  Madhavan Swaminathan ,  George Eugene White

发明人： Michael McAllister ,  Eric Daniel Perfecto ,  James McDonald ,  Keshav Prasad ,  Gordon J. Robbins ,  Chandrika Prasad ,  Madhavan Swaminathan ,  George Eugene White

IPC分类号： H01L21/48 ,  H01L23/538 ,  H05K3/00 ,  H05K3/22 ,  H05K3/46 ,  B05D5/12

CPC分类号： H01L23/5382 ,  H01L21/485 ,  H05K3/225 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K2203/162 ,  H05K3/0082 ,  H05K3/4644

摘要： A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC's, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

摘要翻译： 提供了一种具有定义的修补线的多层薄膜结构和用于修复多层薄膜结构（MLTF）中的互连和/或制造工程电荷（EC）的方法。 该方法包括使用光刻技术（例如直接写入曝光技术）来确定在与结构的顶部金属层相邻的薄膜层处的MLTF中的任何互连缺陷，以限定修复互连所需的顶面连接和/或使EC ，并使用添加剂或阴极金属化技术形成顶表面金属化和修补线。

公开(公告)号：US5916451A

公开(公告)日：1999-06-29

申请号：US450113

申请日：1995-05-25

申请人： Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Gordon Jay Robbins ,  Madhavan Swaminathan ,  George Eugene White

发明人： Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Gordon Jay Robbins ,  Madhavan Swaminathan ,  George Eugene White

IPC分类号： H01L23/538 ,  H05K1/03 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H01B13/00

CPC分类号： H05K1/116 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2924/15312 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/115 ,  H05K2201/0367 ,  H05K3/4007 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/467 ,  Y10S428/901 ,  Y10T428/24926

摘要： A device includes a ceramic substrate. A ceramic via is defined within the ceramic substrate at an actual location which differs from a designed desired location for the ceramic via. A minimal capture pad electrically communicates the actual location with the designed desired location. The minimal capture pad contains a ceramic via contact portion, a thin film stud contact portion, and a connecting portion; and each of the three is configured to be as small as permitted to limit the capacitances produced by the capture pad.

公开(公告)号：US06444919B1

公开(公告)日：2002-09-03

申请号：US08477054

申请日：1995-06-07

申请人： Laertis Economikos ,  Mukta Shaji Farooq ,  Michael Ford McAllister ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Madhavan Swaminathan ,  Thomas Anthony Wassick ,  George White

发明人： Laertis Economikos ,  Mukta Shaji Farooq ,  Michael Ford McAllister ,  Eric Daniel Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Madhavan Swaminathan ,  Thomas Anthony Wassick ,  George White

IPC分类号： H05K103

CPC分类号： H01L23/5382 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0286 ,  H05K1/0289 ,  H05K3/467 ,  H01L2924/00

摘要： A thin film wiring scheme on a substrate. The thin film wiring scheme includes a plurality of chip connection pads at each of a first and second chip site on the substrate, a plurality of directional wiring lines interspersed between the chip connection pads at each of the first and second chip sites, at least one of the directional wiring lines being orthogonal to at least one of the other directional wiring lines at each of the first and second chip sites, and a plurality of chip site interconnection lines connecting directional wiring lines at the first chip site with the directional wiring lines at the second chip site.

摘要翻译： 基板上的薄膜布线方案。 薄膜布线方案包括在基板上的第一和第二芯片位置的每一个处的多个芯片连接焊盘，散布在第一和第二芯片位置中的每一个的芯片连接焊盘之间的多个定向布线，至少一个 所述定向布线与所述第一和第二芯片位置中的每一个处的所述其它方向布线中的至少一个正交;以及多个芯片布线，其将所述第一芯片位置处的方向布线与所述定向布线连接， 第二个芯片站点。

公开(公告)号：US5464682A

公开(公告)日：1995-11-07

申请号：US166424

申请日：1993-12-14

申请人： Eric D. Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Gordon J. Robbins ,  Madhavan Swaminathan ,  George E. White

发明人： Eric D. Perfecto ,  Chandrika Prasad ,  Keshav Prasad ,  Gordon J. Robbins ,  Madhavan Swaminathan ,  George E. White

IPC分类号： H01L23/538 ,  H05K1/03 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  B32B9/00

CPC分类号： H05K1/116 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2924/15312 ,  H05K1/0306 ,  H05K1/113 ,  H05K1/115 ,  H05K2201/0367 ,  H05K3/4007 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/467 ,  Y10S428/901 ,  Y10T428/24926

摘要： A device includes a ceramic substrate. A ceramic via is defined within the ceramic substrate at an actual location which differs from a designed desired location for the ceramic via. A minimal capture pad electrically communicates the actual location with the designed desired location. The minimal capture pad contains a ceramic via contact portion, a thin film stud contact portion, and a connecting portion; and each of the three is configured to be as small as permitted to limit the capacitances produced by the capture pad.

摘要翻译： 一种器件包括陶瓷衬底。 在陶瓷衬底内的陶瓷通孔限定在不同于用于陶瓷通孔的设计的所需位置的实际位置。 最小捕获垫将实际位置与设计的所需位置电连通。 最小捕获垫包含陶瓷通孔接触部分，薄膜螺柱接触部分和连接部分; 并且三个中的每一个被配置为尽可能小以限制由捕获垫产生的电容。

公开(公告)号：US5378927A

公开(公告)日：1995-01-03

申请号：US65385

申请日：1993-05-24

申请人： Michael F. McAllister ,  James A. McDonald ,  Keshav Prasad ,  Gordon J. Robbins ,  Madhavan Swaminathan

发明人： Michael F. McAllister ,  James A. McDonald ,  Keshav Prasad ,  Gordon J. Robbins ,  Madhavan Swaminathan

IPC分类号： H01L23/12 ,  H01L21/768 ,  H01L23/522 ,  H01L23/538 ,  H01L23/50 ,  H01L23/52

CPC分类号： H01L23/5384 ,  H01L23/5386 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011

摘要： A thin-film arrangement for a non-planar structure is described. The structure includes a substrate and a plurality of thin-film layers stacked on top of each other above the substrate. The layers contain conductive patterns and vias that provide connections between the conductive pattern in one of the layers to the conductive pattern in another layer. Vias that provide a connection between the conductive pattern of one layer to the conductive pattern in another remotely located layer are offset and in contact with respect to each other and are positioned in a non-linear arrangement, preferably in the form of a helix or a multiple helix.

摘要翻译： 描述了用于非平面结构的薄膜装置。 该结构包括基板和层叠在基板上方的彼此顶部的多个薄膜层。 这些层包含导电图案和通孔，其提供在一个层中的导电图案与另一层中的导电图案之间的连接。 在另一个位于远的位置的层之间提供一层导电图案与导电图案之间的连接的通孔相对于彼此偏移并接触，并且以非线性排列方式定位，优选为螺旋形或 多重螺旋

公开(公告)号：US5756400A

公开(公告)日：1998-05-26

申请号：US568064

申请日：1995-12-08

申请人： Yan Ye ,  Diana Xiaobing Ma ,  Gerald Zheyao Yin ,  Keshav Prasad ,  Mark Siegel ,  Steve S. Y. Mak ,  Paul Martinez ,  James S. Papanu ,  Danny Chien Lu

发明人： Yan Ye ,  Diana Xiaobing Ma ,  Gerald Zheyao Yin ,  Keshav Prasad ,  Mark Siegel ,  Steve S. Y. Mak ,  Paul Martinez ,  James S. Papanu ,  Danny Chien Lu

IPC分类号： C23F4/00 ,  B08B7/00 ,  H01L21/205 ,  H01L21/302 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/00

CPC分类号： B08B7/0042 ,  Y10S438/905

摘要： The present invention provides an apparatus and process for plasma cleaning the interior surfaces of semiconductor processing chambers. The method is directed to the dry etching of accumulated contaminant residues attached to the inner surfaces of the plasma processing chamber and includes introducing a cleaning gas mixture of a halogen-containing gas; activating a plasma in an environment substantially free of oxygen species; contacting the contaminant residues with the activated cleaning gas to volatilize the residues; and removing the gaseous by-products from the chamber. The etchant gaseous mixture comprises an even or greater amount of at least one fluorine-containing gas and an even or lesser amount of at least one chlorine-containing gas. The instant invention enables the intermittent use of the cleaning steps in an ongoing plasma processing of semiconductor wafers without chamber downtime and significant loss of wafer production.

摘要翻译： 本发明提供了一种用于等离子体清洁半导体处理室内表面的装置和方法。 该方法涉及连接到等离子体处理室的内表面上的累积污染物残留物的干蚀刻，并且包括引入含卤素气体的清洁气体混合物; 在基本上不含氧物质的环境中激活等离子体; 使污染物残留物与活化的清洁气体接触以挥发残余物; 并从室中除去气态副产物。 蚀刻剂气体混合物包含甚至或更多量的至少一种含氟气体和甚至或更少量的至少一种含氯气体。 本发明能够在半导体晶片的持续等离子体处理中间歇地使用清洁步骤，而无需室停机和晶片生产的显着损失。