公开(公告)号：US09406587B2

公开(公告)日：2016-08-02

申请号：US13533655

申请日：2012-06-26

Applicant: Harold Ryan Chase ,  Mihir K. Roy ,  Mathew J. Manusharow ,  Mark Hlad

Inventor： Harold Ryan Chase ,  Mihir K. Roy ,  Mathew J. Manusharow ,  Mark Hlad

IPC: H01L23/48 ,  H01L21/768 ,  H05K1/02 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H05K3/46 ,  H01L23/36

CPC classification number: H01L21/76879 ,  H01L21/288 ,  H01L21/76838 ,  H01L23/00 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/552 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H05K1/0219 ,  H05K1/0222 ,  H05K3/4602 ,  H05K2201/09581 ,  H01L2924/014

Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.

Abstract translation: 示出了基板，半导体器件和方法的实施例，其包括用于改善传导的细长结构。 还示出了延伸的结构和方法，其提供电磁隔离以减少相邻部件中的噪声。

公开(公告)号：US20140179060A1

公开(公告)日：2014-06-26

申请号：US14194936

申请日：2014-03-03

Applicant: Mihir K. Roy ,  Mathew J. Manusharow

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H01L21/48 ,  H01L25/00

CPC classification number: H01L21/4857 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15312 ,  H05K3/007 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2203/0769 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins.

Abstract translation: 无芯针脚阵列（PGA）衬底包括不使用焊料与PGA衬底集成的PGA引脚。 通过在PGA引脚上形成积聚层，使无芯PGA基板集成PGA引脚的过程，使得通孔与PGA引脚的引脚头直接接触。

公开(公告)号：US20130001794A1

公开(公告)日：2013-01-03

申请号：US13174109

申请日：2011-06-30

Applicant: Mihir K. Roy ,  Mathew J. Manusharow

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H01L23/48 ,  H01L21/283

CPC classification number: H01L21/4857 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15312 ,  H05K3/007 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2203/0769 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins.

Abstract translation: 无芯针脚阵列（PGA）衬底包括不使用焊料与PGA衬底集成的PGA引脚。 通过在PGA引脚上形成积聚层，使无芯PGA基板集成PGA引脚的过程，使得通孔与PGA引脚的引脚头直接接触。

公开(公告)号：US09198293B2

公开(公告)日：2015-11-24

申请号：US13743252

申请日：2013-01-16

Applicant: Harold R. Chase ,  Mathew J. Manusharow ,  Mark S. Hlad ,  Mihir K. Roy

Inventor： Harold R. Chase ,  Mathew J. Manusharow ,  Mark S. Hlad ,  Mihir K. Roy

IPC: H01L23/48 ,  H05K1/16 ,  H05K1/02 ,  H01L23/498 ,  H01L23/552 ,  H01L23/64

CPC classification number: H05K1/165 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L23/645 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15311 ,  H05K1/0222

Abstract: Non-cylindrical conducting shapes are described in the context of multilayer laminated substrate cores. In one example a package substrate core includes a plurality of dielectric layers pressed together to form a multilayer core, a conductive bottom pattern on a bottom surface of the multilayer core, and a conductive top pattern on a top surface of the multilayer core. At least one elongated via extends through each layer of the multilayer core, each elongated via containing a conductor and each connected to a conductor of a via in an adjacent layer to electrically connect the top pattern and the bottom pattern through the conductors of the elongated vias.

Abstract translation: 在多层层叠基板芯的上下文中描述非圆柱形导电形状。 在一个示例中，封装衬底芯包括压在一起以形成多层芯的多个电介质层，多层芯的底表面上的导电底部图案，以及多层芯的顶表面上的导电顶部图案。 至少一个细长的通孔延伸穿过多层芯的每个层，每个细长的通孔包含一个导体，并且各自连接到相邻层中的通孔的导体，以通过细长通孔的导体电连接顶部图案和底部图案 。

公开(公告)号：US20140197545A1

公开(公告)日：2014-07-17

申请号：US13743252

申请日：2013-01-16

Applicant: Harold R. Chase ,  Mathew J. Manusharow ,  Mark S. Hlad ,  Mihir K. Roy

Inventor： Harold R. Chase ,  Mathew J. Manusharow ,  Mark S. Hlad ,  Mihir K. Roy

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H05K1/165 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/552 ,  H01L23/645 ,  H01L2223/6622 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15311 ,  H05K1/0222

Abstract: Non-cylindrical conducting shapes are described in the context of multilayer laminated substrate cores. In one example a package substrate core includes a plurality of dielectric layers pressed together to form a multilayer core, a conductive bottom pattern on a bottom surface of the multilayer core, and a conductive top pattern on a top surface of the multilayer core. At least one elongated via extends through each layer of the multilayer core, each elongated via containing a conductor and each connected to a conductor of a via in an adjacent layer to electrically connect the top pattern and the bottom pattern through the conductors of the elongated vias.

Abstract translation: 在多层层叠基板芯的上下文中描述非圆柱形导电形状。 在一个示例中，封装衬底芯包括压在一起以形成多层芯的多个电介质层，多层芯的底表面上的导电底部图案，以及多层芯的顶表面上的导电顶部图案。 至少一个细长的通孔延伸穿过多层芯的每个层，每个细长的通孔包含一个导体，并且各自连接到相邻层中的通孔的导体，以通过细长通孔的导体电连接顶部图案和底部图案 。

公开(公告)号：US20140175636A1

公开(公告)日：2014-06-26

申请号：US13722128

申请日：2012-12-20

Applicant: Mihir K. Roy ,  Mathew J. Manusharow

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/147 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/25 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13101 ,  H01L2224/1412 ,  H01L2224/14505 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/1712 ,  H01L2224/24146 ,  H01L2224/2541 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15747 ,  H01L2924/381 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.

Abstract translation: 描述了通过直接芯片连接（DCA）实现微电子管芯和母板之间的高密度和低密度互连的实施例。 在一些实施例中，微电子管芯具有高密度互连，其具有沿着一个边缘设置的小凸起间距，以及较低密度的连接区域，其具有位于管芯的其它区域中的较大的凸起间距。 芯片之间的高密度互连区域使用由能够支持其中制造的高密度互连（例如硅）的材料制成的互连桥互连。 较低密度的连接区域用于使用DCA将互连的管芯直接连接到电路板上。 当互连芯片与互连桥相互连接时，高密度互连可以利用电流控制折叠芯片连接（C4）间隔，同时在电路板上允许更大的间隔。

公开(公告)号：US20140160675A1

公开(公告)日：2014-06-12

申请号：US13709824

申请日：2012-12-10

Applicant: Mihir K. Roy ,  Mathew J. Manusharow

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H01L27/04 ,  H01L21/02 ,  G06F1/16

CPC classification number: H01L21/02 ,  G06F1/1658 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/50 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/83815 ,  H01L2924/1461 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Embodiments of systems, devices, and methods to minimize warping of ultrathin IC packaged products are generally described herein. In some embodiments, an apparatus includes an IC mounted on a package substrate, and a capacitive stiffener subassembly mounted on the package substrate. The capacitive stiffener subassembly includes a plurality of capacitive elements electrically connected to contacts of the IC.

Abstract translation: 本文通常描述用于最小化超薄IC封装产品的翘曲的系统，装置和方法的实施例。 在一些实施例中，一种装置包括安装在封装衬底上的IC和安装在封装衬底上的电容强化子组件。 电容式加强件子组件包括电连接到IC的触点的多个电容元件。

公开(公告)号：US20140159850A1

公开(公告)日：2014-06-12

申请号：US13711149

申请日：2012-12-11

Applicant: Mihir K. Roy ,  Mathew J. Manusharow ,  Harold Ryan Chase

Inventor： Mihir K. Roy ,  Mathew J. Manusharow ,  Harold Ryan Chase

IPC: H01F5/00

CPC classification number: H01F17/0013 ,  H01F2017/0066

Abstract: A method and device includes a first conductor formed on a first dielectric layer as a partial turn of a coil. A second conductor is formed on a second dielectric layer that covers the first dielectric layer and first conductor, the second conductor forming a partial turn of the coil. A vertical interconnect couples the first and second conductors to form a first full turn of the coil. The interconnect coupling can be enhanced by embedding some selective magnetic materials into the substrate.

Abstract translation: 一种方法和装置包括形成在作为线圈的部分转弯的第一介电层上的第一导体。 第二导体形成在覆盖第一介电层和第一导体的第二介电层上，第二导体形成线圈的部分转弯。 垂直互连将第一和第二导体耦合以形成线圈的第一整圈。 可以通过将一些选择性磁性材料嵌入衬底来增强互连耦合。

公开(公告)号：US20170178786A1

公开(公告)日：2017-06-22

申请号：US14973115

申请日：2015-12-17

Applicant: William J. Lambert ,  Mihir K. Roy ,  Mathew J. Manusharow ,  Yikang Deng

Inventor： William J. Lambert ,  Mihir K. Roy ,  Mathew J. Manusharow ,  Yikang Deng

IPC: H01F27/28 ,  H01F41/04 ,  C25D5/16 ,  C25D7/00 ,  C25D5/48 ,  H01F27/255 ,  H01F41/02

CPC classification number: H01F27/2804 ,  C25D5/16 ,  C25D5/48 ,  C25D7/00 ,  H01F17/0013 ,  H01F17/0033 ,  H01F27/255 ,  H01F41/0206 ,  H01F41/041 ,  H01F41/046 ,  H01F2017/002 ,  H01F2027/2809

Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.

公开(公告)号：US09622350B2

公开(公告)日：2017-04-11

申请号：US14040637

申请日：2013-09-28

Applicant: Mihir K. Roy ,  Mathew J. Manusharow

Inventor： Mihir K. Roy ,  Mathew J. Manusharow

IPC: H05K1/14 ,  H05K3/20 ,  H05K3/00 ,  H05K3/10 ,  H05K3/18

CPC classification number: H05K1/116 ,  H05K1/141 ,  H05K1/181 ,  H05K3/0026 ,  H05K3/107 ,  H05K3/182 ,  H05K3/207 ,  H05K3/422 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49128

Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.