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43 条记录 (耗时 0.047 秒)

    Method for multiple spacer width control
    2.
    发明授权
    Method for multiple spacer width control 有权
    多间隔宽度控制方法

    公开(公告)号：US07176137B2

    公开(公告)日：2007-02-13

    申请号：US10435009

    申请日：2003-05-09

    申请人： Baw-Ching Perng ,  Yih-Shung Lin ,  Ming-Ta Lei ,  Ai-Sen Liu ,  Chia-Hui Lin ,  Cheng-Chung Lin

    发明人： Baw-Ching Perng ,  Yih-Shung Lin ,  Ming-Ta Lei ,  Ai-Sen Liu ,  Chia-Hui Lin ,  Cheng-Chung Lin

    IPC分类号： H01L21/302

    CPC分类号： H01L29/6656 ,  H01L21/823468

    摘要： A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

    摘要翻译： 形成多个栅极侧壁间隔物的方法，每个栅极侧壁间隔件包括不同的相关栅极侧壁间隔物宽度，包括提供第一多个栅极结构; 在第一多个栅极结构上覆盖沉积第一介电层; 在第一介电层上铺设第二介电层; 通过第一和第二介电层的厚度回蚀; 覆盖沉积第一光致抗蚀剂层以覆盖第一多个并且图案化以选择性地暴露至少第二多个栅极结构; 对所述至少第二多个栅极结构进行各向同性蚀刻预定的时间段以选择性地蚀刻掉所述第一介电层的预定部分; 并且选择性地蚀刻掉第二介电层以留下包括多个相关联的侧壁间隔物宽度的栅极结构。

    Method for forming multiple spacer widths
    7.
    发明授权
    Method for forming multiple spacer widths 失效
    形成多个间隔物宽度的方法

    公开(公告)号：US07011929B2

    公开(公告)日：2006-03-14

    申请号：US10340245

    申请日：2003-01-09

    申请人： Ming-Ta Lei ,  Yih-Shung Lin ,  Ai-Sen Liu ,  Cheng-Chung Lin ,  Baw-Ching Perng ,  Chia-Hui Lin

    发明人： Ming-Ta Lei ,  Yih-Shung Lin ,  Ai-Sen Liu ,  Cheng-Chung Lin ,  Baw-Ching Perng ,  Chia-Hui Lin

    IPC分类号： H01L21/302

    CPC分类号： H01L21/823468

    摘要： A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a plurality of gate structures formed overlying a substrate and a plurality of dielectric layers formed substantially conformally overlying the gate structures; exposing a first selected portion of the plurality followed by anisotropically etching through a thickness portion comprising at least the uppermost dielectric layer to form a first sidewall spacer width; exposing a first subsequent selected portion of the plurality followed by etching through at least a thickness portion of the uppermost dielectric layer; and, exposing a second subsequent selected portion of the plurality followed by anisotropically etching through at least a thickness portion of the uppermost dielectric layer to form a subsequent sidewall spacer width.

    摘要翻译： 一种形成多个栅极侧壁间隔物的方法，每个栅极侧壁间隔件包括不同的相关栅极侧壁间隔物宽度，包括提供形成在衬底上的多个栅极结构和基本上共形地覆盖栅极结构的多个电介质层; 暴露多个的第一选定部分，然后通过各向异性蚀刻穿过包括至少最上面的介电层的厚度部分以形成第一侧壁间隔物宽度; 暴露多个的第一后续选定部分，然后蚀刻通过至少最上层介电层的厚度部分; 并且暴露多个随后的第二部分，然后通过各向异性蚀刻穿过至少最上面的介电层的厚度部分以形成随后的侧壁间隔物宽度。

    Surface treatment of metal interconnect lines
    8.
    发明授权
    Surface treatment of metal interconnect lines 有权
    金属互连线的表面处理

    公开(公告)号：US08053894B2

    公开(公告)日：2011-11-08

    申请号：US11213238

    申请日：2005-08-26

    申请人： Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Ta Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

    发明人： Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Ta Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

    IPC分类号： H01L23/48

    CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76886

    摘要： Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

    摘要翻译： 用于形成半导体结构的装置，其包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。 导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层） 相互作用形成合金层。 合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。

    Surface treatment of metal interconnect lines
    9.
    发明申请
    Surface treatment of metal interconnect lines 有权
    金属互连线的表面处理

    公开(公告)号：US20060001160A1

    公开(公告)日：2006-01-05

    申请号：US11213238

    申请日：2005-08-26

    申请人： Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Ta Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

    发明人： Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Ta Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

    IPC分类号： H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  B32B15/00 ,  B32B17/06

    CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76886

    摘要： Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

    摘要翻译： 用于形成半导体结构的装置，其包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。 导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层） 相互作用形成合金层。 合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。