公开(公告)号：US4893174A

公开(公告)日：1990-01-09

申请号：US240443

申请日：1988-09-02

申请人： Minoru Yamada ,  Akira Masaki ,  Kazuo Sato ,  Yutaka Harada

发明人： Minoru Yamada ,  Akira Masaki ,  Kazuo Sato ,  Yutaka Harada

IPC分类号： H01L21/768 ,  H01L23/473 ,  H01L23/48 ,  H01L25/065

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/473 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/10158

摘要： An integrated circuit is disclosed in which a plurality of semiconductor substrates are stacked in such a manner that an insulating board, provided with (1) structure, such as grooves, for transmitting a coolant so as to dissipate heat, and (2) an electrical interconnection member for electrically connecting adjacent semiconductor substrates, is sandwiched between semiconductor substrates. In order to attain the high-speed signal transmission between a semiconductor substrate and an insulating board, a signal current flows not only in a main surface of the semiconductor substrate but also in directions perpendicular to the main surface. The insulating board may be formed of an insulating silicon carbide plate which has a plurality of grooves filled with a metal.

摘要翻译： 公开了一种集成电路，其中多个半导体衬底以这样的方式堆叠，即：设置有（1）结构的绝缘板，例如沟槽，用于传输冷却剂以散热;以及（2）电气 用于电连接相邻半导体衬底的互连构件被夹在半导体衬底之间。 为了实现半导体衬底和绝缘板之间的高速信号传输，信号电流不仅在半导体衬底的主表面中而且在与主表面垂直的方向上流动。 绝缘板可以由具有填充有金属的多个槽的绝缘碳化硅板形成。

公开(公告)号：US4644385A

公开(公告)日：1987-02-17

申请号：US665548

申请日：1984-10-26

申请人： Keiichirou Nakanishi ,  Minoru Yamada ,  Akira Masaki ,  Kuninori Imai ,  Katuaki Chiba

发明人： Keiichirou Nakanishi ,  Minoru Yamada ,  Akira Masaki ,  Kuninori Imai ,  Katuaki Chiba

IPC分类号： H01L23/433 ,  H01L23/473 ,  H01L25/04

CPC分类号： H01L23/473 ,  H01L23/4332 ,  H01L2224/16

摘要： This invention concerns a cooling module for integrated circuit chips, characterized in that it is provided with cooling members through which a coolant circulates, and which are connected directly, or via insulating plates, to a plurality of integrated circuit chips mounted on a wiring substrate, and pipes which introduce the coolant into the cooling members and which have a resiliency which is high enough to enable the pipes to expand and contract in the direction perpendicular to the wiring substrate.

摘要翻译： 本发明涉及一种用于集成电路芯片的冷却模块，其特征在于，其具有冷却元件，冷却器通过该冷却元件循环并直接连接或经由绝缘板连接到安装在布线基板上的多个集成电路芯片， 以及将冷却剂引入冷却部件中并且具有足够高的弹性以使管能够在垂直于布线基板的方向膨胀和收缩的管道。

公开(公告)号：US4686606A

公开(公告)日：1987-08-11

申请号：US827613

申请日：1986-02-10

申请人： Minoru Yamada ,  Mitsuru Usui ,  Akira Masaki ,  Keiichirou Nakanishi ,  Masahide Tokuda

发明人： Minoru Yamada ,  Mitsuru Usui ,  Akira Masaki ,  Keiichirou Nakanishi ,  Masahide Tokuda

IPC分类号： H01L23/473 ,  H01L21/58 ,  H01L23/36 ,  H01L23/373 ,  H01L23/433 ,  H05K7/20

CPC分类号： H01L24/83 ,  H01L23/3736 ,  H01L23/4332 ,  H01L24/29 ,  H01L2224/16225 ,  H01L2224/29109 ,  H01L2224/29191 ,  H01L2224/73253 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/16152

摘要： A cooling structure for cooling a multichip module for effectively removing heat generated from integrated circuit chips. A suction plate formed with minute grooves on one of its surfaces is disposed between each integrated circuit chip and an associated cooling block and is brought into contact at a grooved surface with the integrated circuit chip through a layer of a liquid such as silicone oil interposed therebetween, thereby producing negative hydrostatic pressure by capillary action of the minute grooves. The suction plate has a thickness small enough to be bent under influence of the negative hydrostatic pressure to follow a warping of the integrated circuit chip, so that the clearance between the opposing surfaces of the suction plate and the integrated circuit chip can be minimized. Thus, an integrated circuit chip cooling device of surface-to-surface contact type operable with a low thermal resistance is provided, which can improve the maintainability and reliability without sacrificing the cooling efficiency.

摘要翻译： 一种用于冷却多芯片模块的冷却结构，用于有效地去除由集成电路芯片产生的热量。 在其一个表面上形成有微小凹槽的吸盘设置在每个集成电路芯片和相关联的冷却块之间，并且在沟槽表面与集成电路芯片通过一层液体（例如插入其间的硅油）接触 ，从而通过微小凹槽的毛细管作用产生负静压。 吸盘的厚度足够小以在负静压力的影响下弯曲，以跟随集成电路芯片的翘曲，使得吸板和集成电路芯片的相对表面之间的间隙可以最小化。 因此，提供了以低热阻可操作的表面接触型的集成电路芯片冷却装置，这可以在不牺牲冷却效率的情况下提高可维护性和可靠性。

公开(公告)号：US5214318A

公开(公告)日：1993-05-25

申请号：US638568

申请日：1991-01-07

申请人： Keiichirou Nakanishi ,  Mararu Osanai ,  Minoru Yamada ,  Masakazu Yamamoto ,  Akira Masaki ,  Mitsuo Usami

发明人： Keiichirou Nakanishi ,  Mararu Osanai ,  Minoru Yamada ,  Masakazu Yamamoto ,  Akira Masaki ,  Mitsuo Usami

IPC分类号： H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H03F3/45 ,  H03K5/151 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/018 ,  H04B3/00

CPC分类号： H03K5/151 ,  H03K19/0136 ,  H03K19/01831 ,  H01L2924/0002

摘要： A semiconductor integrated circuit device has, in one embodiment, a pair of signal transmission lines formed over and insulated from a semiconductor substrate, a first circuit formed in the semiconductor substrate and electrically connected with one end of the pair of signal transmission lines for sending an electric signal, and a second circuit formed in the semiconductor substrate and electrically connected with the other end of the pair of signal transmission lines for receiving the electric signal propagating over the transmission line pair. A control resistance is electrically connected between the pair of transmission lines at the above-mentioned other end for controlling a delay time of the signal propagating over the pair of signal transmission lines between the opposite ends of the pair of signal transmission lines.

摘要翻译： 在一个实施例中，半导体集成电路器件具有形成在半导体衬底上并与其绝缘的一对信号传输线，形成在半导体衬底中并与该对信号传输线的一端电连接的第一电路，用于发送 电信号和形成在半导体衬底中并与该对信号传输线的另一端电连接的第二电路，用于接收在传输线对上传播的电信号。 控制电阻电连接在上述另一端的一对传输线之间，用于控制在一对信号传输线的相对端之间在一对信号传输线上传播的信号的延迟时间。

公开(公告)号：US5165010A

公开(公告)日：1992-11-17

申请号：US461080

申请日：1990-01-04

申请人： Noboru Masuda ,  Moritoshi Yasunaga ,  Minoru Yamada ,  Akira Masaki ,  Mitsuo Asai ,  Yuzo Hirai ,  Masayoshi Yagyu ,  Takehisa Hayashi ,  Toshio Doi ,  Kenichi Ishibashi

发明人： Noboru Masuda ,  Moritoshi Yasunaga ,  Minoru Yamada ,  Akira Masaki ,  Mitsuo Asai ,  Yuzo Hirai ,  Masayoshi Yagyu ,  Takehisa Hayashi ,  Toshio Doi ,  Kenichi Ishibashi

IPC分类号： G06N3/04 ,  G06N3/063

CPC分类号： G06N3/063 ,  G06N3/04

摘要： An information processing system includes a plurality of functional blocks (neurons) and a data bus for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional blocks (neuron) having the own address designated by the address signal supplied through an address bus outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the address signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

公开(公告)号：US4710854A

公开(公告)日：1987-12-01

申请号：US24894

申请日：1987-03-10

申请人： Minoru Yamada ,  Motoyo Wajima ,  Akira Masaki ,  Akio Takahashi ,  Keiichirou Nakanishi ,  Katuo Sugawara

发明人： Minoru Yamada ,  Motoyo Wajima ,  Akira Masaki ,  Akio Takahashi ,  Keiichirou Nakanishi ,  Katuo Sugawara

IPC分类号： H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H05K1/14

CPC分类号： H05K3/4626 ,  H05K1/024 ,  H05K1/0237 ,  H05K1/0346 ,  H05K1/115 ,  H05K2201/015 ,  H05K2201/0158 ,  H05K2201/0191 ,  H05K2201/09327 ,  H05K2201/09536 ,  H05K3/4623

摘要： A multilayer wiring board structure includes a plurality of conductor layers and insulation layers interleaved between each ones of the conductor layers. The conductor layers includes power (or ground) line layers and signal line layers, and one type of insulation layer having lower relative permittivity and another type of insulation layer having higher relative permittivity is used between power (ground) line layers interposed by signal line layer(s).

摘要翻译： 多层布线板结构包括在每个导体层之间交错的多个导体层和绝缘层。 导体层包括功率（或接地）线层和信号线层，并且在由信号线层插入的功率（接地）线层之间使用具有较低相对介电常数的一种类型的绝缘层和具有较高相对介电常数的另一种类型的绝缘层 （s）。

公开(公告)号：US4558395A

公开(公告)日：1985-12-10

申请号：US604003

申请日：1984-04-26

申请人： Minoru Yamada ,  Akira Masaki ,  Masakazu Yamamoto ,  Keiichirou Nakanishi ,  Takashi Nishida ,  Takahiro Daikoku ,  Fumiyuki Kobayashi ,  Kuninori Imai

发明人： Minoru Yamada ,  Akira Masaki ,  Masakazu Yamamoto ,  Keiichirou Nakanishi ,  Takashi Nishida ,  Takahiro Daikoku ,  Fumiyuki Kobayashi ,  Kuninori Imai

IPC分类号： H01L23/36 ,  H01L23/433 ,  H01L23/473 ,  H05K7/20

CPC分类号： H01L23/4332 ,  H01L2224/16225

摘要： A cooling module for integrated circuit chips comprising a plurality of integrated circuit chips mounted on a wiring substrate, cooling members respectively provided for integrated circuit chips, each of the cooling members having therein space for circulating the coolant, and flexible pipes connected to respective cooling members, the coolant being caused to flow into or out of said space of said cooling member through the flexible pipes in order to remove heat from the integrated circuit chip.

摘要翻译： 一种用于集成电路芯片的冷却模块，包括安装在布线基板上的多个集成电路芯片，分别设置用于集成电路芯片的冷却构件，每个冷却构件具有用于使冷却剂循环的空间，以及连接到各个冷却构件的柔性管道 通过柔性管使冷却剂流入或流出所述冷却构件的所述空间，以便从集成电路芯片去除热量。

公开(公告)号：US4723082A

公开(公告)日：1988-02-02

申请号：US884896

申请日：1986-07-14

申请人： Michio Asano ,  Akira Masaki ,  Masaru Osani ,  Minoru Yamada ,  Kenichi Ishibashi ,  Noboru Masuda

发明人： Michio Asano ,  Akira Masaki ,  Masaru Osani ,  Minoru Yamada ,  Kenichi Ishibashi ,  Noboru Masuda

IPC分类号： H01L27/00 ,  H01L21/3205 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H03K19/0185 ,  H03K19/017 ,  H03K19/094

CPC分类号： H03K19/018521 ,  H03K19/018557

摘要： A laminated multilayer electric circuit is comprised of wafers having each internal electric circuits and laminated one after another. A signal transfer circuit used in the laminated multilayer electric circuit for transfer of signals between the wafers through an electrostatic capacitor has a receiving circuit of sufficiently high input resistance for receiving a signal from a capacitance electrode forming the electrostatic capacitor, and a circuit for clamping the level of the signal substantially within the input amplitude for the receiving circuit. The signal transfer circuit permits the signal transfer to be performed not through a flip-flop or the like and consequently at high speeds.

摘要翻译： 叠层多层电路由具有每个内部电路并且彼此层叠的晶片组成。 在用于通过静电电容器在晶片之间传递信号的叠层多层电路中使用的信号传输电路具有足够高的输入电阻的接收电路，用于从形成静电电容器的电容电极接收信号，以及用于钳位 信号的电平基本上在接收电路的输入幅度内。 信号传送电路允许不通过触发器等执行信号传送，并且因此以高速执行信号传送。

公开(公告)号：US20090009215A1

公开(公告)日：2009-01-08

申请号：US11596011

申请日：2005-03-28

申请人： Yohei Matsumoto ,  Akira Masaki

发明人： Yohei Matsumoto ,  Akira Masaki

IPC分类号： H03K19/177 ,  G06F17/50

CPC分类号： H03K19/17736 ,  H01L27/11803 ,  H03K19/17796

摘要： An FPGA needs extremely large numbers of switches in its wiring architecture and therefore shows low logic density and low operating speed. This tendency becomes increasingly evident with high integration FPGAs. 3-dimensional FPGAs are getting attention for potential improvements in their operating speed and logic density. However, 3-dimensional integration processes have poor yield and are difficult to adapt for the production of devices with fine features. In addition, difficulty in heat radiation imposes limits on the number of stacks. The present invention exploits advantages of the 3-dimensional FPGA to deliver FPGAs with high speed/high integration and which resolves difficulty in manufacturing processes. The present invention solves problems by proposing a design method for an FPGA in which a high dimensional FPGA switch topology is embedded in a lower dimensional integrated circuit and a semiconductor integrated circuit including an FPGA in which a high dimensional FPGA switch topology is embedded in a lower dimensional integrated circuit.

摘要翻译： FPGA在其布线架构中需要极大数量的开关，因此显示出低的逻辑密度和低的运行速度。 高集成度FPGA的趋势越来越明显。 3维FPGA正在注意其运行速度和逻辑密度的潜在改进。 然而，三维一体化处理成品率低，难以适应具有精细特征的装置的生产。 此外，热辐射的困难对堆叠数量施加了限制。 本发明利用3维FPGA的优点来提供高速/高集成度的FPGA，并且解决了制造过程中的难度。 本发明通过提出一种用于FPGA的设计方法来解决问题，其中高维FPGA开关拓扑嵌入在低维集成电路中，以及包括FPGA的半导体集成电路，其中高维FPGA开关拓扑嵌入在较低维数 三维集成电路。

公开(公告)号：US07217233B2

公开(公告)日：2007-05-15

申请号：US11116368

申请日：2005-04-28

申请人： Akira Masaki ,  Takao Watanabe

发明人： Akira Masaki ,  Takao Watanabe

IPC分类号： B31F1/08

CPC分类号： B65H45/167 ,  B65H29/52 ,  B65H2404/693

摘要： A parallel folding apparatus of a folding machine comprises a first cylinder in contact with a second cylinder. A guide plate guides a signature transported on the lower circumferential surface of the second cylinder after being double-folded by grippers of the second cylinder in cooperation with knives of the first cylinder. The guide plate comprises a stationary guide located downstream, in the rotating direction, of the point of contact between the first cylinder and the second cylinder and disposed continuously along the circumferential surfaces of the first cylinder and the second cylinder, and a moving guide movable in accordance with the operating speed of the folding machine between a position, closer to the circumferential surface of the first cylinder than the stationary guide, and a position, more remote from the circumferential surface of the first cylinder than the stationary guide.

摘要翻译： 折叠机的平行折叠装置包括与第二气缸接触的第一气缸。 与第一气缸的刀片协作，引导板引导在第二气缸的夹持器双重折叠之后在第二气缸的下圆周表面上传送的标记。 引导板包括位于第一气缸和第二气缸之间的接触点的沿旋转方向的下游并沿着第一气缸和第二气缸的周向表面连续设置的静止引导件，以及可移动的移动引导件 根据折叠机在比第一圆柱体的圆周表面更靠近固定导轨的位置之间的操作速度以及比第一圆柱体的圆周表面更远离静止导轨的位置。