公开(公告)号：US20100018633A1

公开(公告)日：2010-01-28

申请号：US12408366

申请日：2009-03-20

Applicant: Myung-Sam KANG ,  Jung-Hyun PARK ,  Jeong-Woo PARK ,  Ji-Eun KIM

Inventor： Myung-Sam KANG ,  Jung-Hyun PARK ,  Jeong-Woo PARK ,  Ji-Eun KIM

IPC: B32B37/00

CPC classification number: B32B38/04 ,  B32B38/10 ,  B32B2038/0092 ,  B32B2038/047 ,  B32B2309/105 ,  B32B2310/0843 ,  B32B2457/08 ,  H05K3/0035 ,  H05K3/108 ,  H05K3/421 ,  H05K3/428 ,  H05K3/4652 ,  H05K2201/0376 ,  H05K2203/0384 ,  H05K2203/0554 ,  Y10T156/1056 ,  Y10T156/1057 ,  Y10T156/1064 ,  Y10T156/1082

Abstract: Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for connecting one layer to another layer can include forming a circuit pattern on one surface of a carrier; processing a hole corresponding to the via on one surface of the carrier; compressing the surface of the carrier into one surface of an insulation body; removing the carrier; processing a via hole on the insulation body, corresponding to a position of the hole; and forming a conductive material in the via hole, to thereby easily process a hole for forming a via and have high design freedom

Abstract translation: 公开了印刷电路板的制造方法。 制造具有用于将一层连接到另一层的通路的印刷电路板的制造方法可以包括在载体的一个表面上形成电路图案; 在载体的一个表面上处理与通孔对应的孔; 将载体的表面压缩到绝缘体的一个表面中; 移除载体; 处理绝缘体上的通孔，对应于孔的位置; 并且在通孔中形成导电材料，从而容易地加工用于形成通孔的孔，并且具有高的设计自由度

公开(公告)号：US20120244662A1

公开(公告)日：2012-09-27

申请号：US13491279

申请日：2012-06-07

Applicant: Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim ,  Young-Hwan Shin ,  Kyung-Ro Yoon

Inventor： Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim ,  Young-Hwan Shin ,  Kyung-Ro Yoon

IPC: H01L21/50

CPC classification number: H05K3/00 ,  H01L2224/16225 ,  H05K3/30 ,  Y10T29/49124

Abstract: A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the single-layer board on chip package substrate includes an insulator, a circuit pattern and a flip-chip bonding pad, which are formed on an upper surface of the insulator, a conductive bump, which is in contact with a lower surface of the circuit pattern and penetrates through the insulator, a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the flip-chip bonding pad is exposed, and a flip-chip bonding bump, which is formed on an upper surface of the flip-chip bonding pad in order to make a flip-chip connection with an electronic component.

Abstract translation: 公开了一种单层片上封装衬底及其制造方法。 根据本发明的实施例，片上封装衬底上的单层板包括形成在绝缘体上表面上的绝缘体，电路图案和倒装焊接焊盘，导体凸块， 与电路图案的下表面接触并穿透绝缘体，阻焊层，其形成在绝缘体的上表面上，使得至少一部分倒装芯片接合焊盘露出，并且 倒装芯片焊接凸块，其形成在倒装焊盘的上表面上，以便与电子部件进行倒装芯片连接。

公开(公告)号：US20110110058A1

公开(公告)日：2011-05-12

申请号：US12748082

申请日：2010-03-26

Applicant: Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim ,  Young-Hwan Shin ,  Kyung-Ro Yoon

Inventor： Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim ,  Young-Hwan Shin ,  Kyung-Ro Yoon

IPC: H05K7/02 ,  H05K3/00

CPC classification number: H05K3/00 ,  H01L2224/16225 ,  H05K3/30 ,  Y10T29/49124

Abstract: A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the single-layer board on chip package substrate includes an insulator, a circuit pattern and a flip-chip bonding pad, which are formed on an upper surface of the insulator, a conductive bump, which is in contact with a lower surface of the circuit pattern and penetrates through the insulator, a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the flip-chip bonding pad is exposed, and a flip-chip bonding bump, which is formed on an upper surface of the flip-chip bonding pad in order to make a flip-chip connection with an electronic component.

Abstract translation: 公开了一种单层片上封装衬底及其制造方法。 根据本发明的实施例，片上封装衬底上的单层板包括形成在绝缘体上表面上的绝缘体，电路图案和倒装焊接焊盘，导体凸块， 与电路图案的下表面接触并穿透绝缘体，阻焊层，其形成在绝缘体的上表面上，使得至少一部分倒装芯片接合焊盘露出，并且 倒装芯片焊接凸块，其形成在倒装焊盘的上表面上，以便与电子部件进行倒装芯片连接。

公开(公告)号：US20110100952A1

公开(公告)日：2011-05-05

申请号：US12892047

申请日：2010-09-28

Applicant: Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim

Inventor： Ji-Eun KIM ,  Nam-Keun Oh ,  Jung-Hyun Park ,  Young-Ji Kim ,  Jong-Gyu Choi ,  Sang-Duck Kim

IPC: H05K3/06

CPC classification number: H05K3/4007 ,  H05K3/061 ,  H05K3/205 ,  H05K2201/0367 ,  H05K2203/0152 ,  H05K2203/0376

Abstract: A method of manufacturing a printed circuit board having a bump is disclosed. The method includes preparing a first carrier having a first circuit formed thereon, compressing the first carrier to one surface of an insulation layer such that the first circuit is buried, stacking an etching resist on the first carrier in accordance with where the bump is to be formed and forming the bump by etching the first carrier. In accordance with an embodiment of the present invention, the difference in height between a bump and its adjacent bump in a printed circuit board can be reduced, and thus electrical connection between an electronic component and the printed circuit board can be better implemented.

Abstract translation: 公开了一种制造具有凸块的印刷电路板的方法。 该方法包括制备其上形成有第一电路的第一载体，将第一载体压缩到绝缘层的一个表面，使得第一电路被掩埋，根据凸点将在第一载体上堆叠抗蚀剂 通过蚀刻第一载体形成和形成凸块。 根据本发明的实施例，可以减小印刷电路板中的凸块与其相邻凸块之间的高度差，从而可以更好地实现电子部件和印刷电路板之间的电连接。

公开(公告)号：US20100151393A1

公开(公告)日：2010-06-17

申请号：US12636202

申请日：2009-12-11

Applicant: Sang-Ouk KIM ,  Seong-Jun JEONG ,  Su-Mi LEE ,  Bong-Hoon KIM ,  Ji-Eun KIM ,  Jae-Ho YOU ,  Moon-Gyu LEE ,  Seung-Ho NAM

Inventor： Sang-Ouk KIM ,  Seong-Jun JEONG ,  Su-Mi LEE ,  Bong-Hoon KIM ,  Ji-Eun KIM ,  Jae-Ho YOU ,  Moon-Gyu LEE ,  Seung-Ho NAM

IPC: G03F7/20

CPC classification number: B81C1/00031 ,  B81C2201/0149

Abstract: According to an example embodiment of the present invention, a photoresist pattern is formed on a base substrate including a neutral layer. A sacrifice structure including a first sacrifice block and a second sacrifice block is formed on the base substrate having the photoresist pattern, and the sacrifice structure is formed from a first thin film including a first block copolymer. Thus, a chemical pattern is formed to form a nano-structure. Therefore, the nano-structure may be easily formed on a substrate having a large size by using a block copolymer, and productivity and manufacturing reliability may be improved.

Abstract translation: 根据本发明的示例性实施例，在包括中性层的基底基板上形成光致抗蚀剂图案。 在具有光致抗蚀剂图案的基底上形成包括第一牺牲块和第二牺牲块的牺牲结构，牺牲结构由包括第一嵌段共聚物的第一薄膜形成。 因此，形成化学图案以形成纳米结构。 因此，可以通过使用嵌段共聚物容易地在具有大尺寸的基板上形成纳米结构，并且可以提高生产率和制造可靠性。

公开(公告)号：US20120018879A1

公开(公告)日：2012-01-26

申请号：US12981386

申请日：2010-12-29

Applicant: Hee-Min SHIN ,  Cheol-Ho JOH ,  Eun-Hye DO ,  Ji-Eun KIM ,  Kyu-Won LEE

Inventor： Hee-Min SHIN ,  Cheol-Ho JOH ,  Eun-Hye DO ,  Ji-Eun KIM ,  Kyu-Won LEE

IPC: H01L25/11 ,  H01L21/98

CPC classification number: H01L25/50 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/5389 ,  H01L24/18 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/117 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00

Abstract: A stack package includes a cover film, a first package having a first semiconductor chip which is attached to the cover film, a first adhesive member which is formed to seal the first semiconductor chip and a surface of the cover film, and a first circuit pattern which is disposed over the first adhesive member and electrically connected with the first semiconductor chip; a second package disposed over the first package, having a second semiconductor chip which is electrically connected with the first circuit pattern, a second adhesive member which is formed to seal the second semiconductor chip, and a second circuit pattern which is formed over the second adhesive member, and a via formed to pass through the second circuit pattern and the second adhesive member and to be electrically connected with the first circuit pattern and the second circuit pattern.

Abstract translation: 叠层封装包括覆盖膜，具有附接到覆盖膜的第一半导体芯片的第一封装，形成为密封第一半导体芯片的第一粘合构件和覆盖膜的表面，以及第一电路图案 其设置在第一粘合构件上并与第一半导体芯片电连接; 第二封装，设置在所述第一封装上，具有与所述第一电路图案电连接的第二半导体芯片，形成为密封所述第二半导体芯片的第二粘合构件，以及形成在所述第二粘合剂上的第二电路图案 以及形成为穿过第二电路图案和第二粘合构件并且与第一电路图案和第二电路图案电连接的通孔。