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    lll-phosphide light emitting devices with thin active layers
    1.
    发明授权
    lll-phosphide light emitting devices with thin active layers 有权
    具有薄活性层的磷化铟发光器件

    公开(公告)号：US07087941B2

    公开(公告)日：2006-08-08

    申请号：US10011521

    申请日：2001-11-05

    申请人： Nathan F. Gardner ,  Fred A. Kish ,  Herman C. Chui ,  Stephen A. Stockman ,  Michael R. Krames ,  Gloria E. Hofler ,  Christopher Kocot ,  Nicolas J. Moll ,  Tun-Sein Tan

    发明人： Nathan F. Gardner ,  Fred A. Kish ,  Herman C. Chui ,  Stephen A. Stockman ,  Michael R. Krames ,  Gloria E. Hofler ,  Christopher Kocot ,  Nicolas J. Moll ,  Tun-Sein Tan

    IPC分类号： H01L31/72

    CPC分类号： H01L33/30 ,  H01L33/02 ,  H01L33/305

    摘要： The extraction efficiency of a light emitting device can be improved by making the absorbing device layers as thin as possible. The internal quantum efficiency decreases as the device layers become thinner. An optimal active layer thickness balances both effects. An AlGaInP LED includes a substrate and device layers including an AlGaInP lower confining layer of a first conductivity type, an AlGaInP active region of a second conductivity type, and an AlGaInP upper confining layer of a second conductivity type. The absorbance of the active region is at least one fifth of the total absorbance in the light-emitting device. The device optionally includes at least one set-back layers of AlGaInP interposing one of confining layer and active region. The p-type upper confining layer may be doped with oxygen improve the reliability.

    摘要翻译： 通过使吸收装置层尽可能薄，可以提高发光装置的提取效率。 内部量子效率随着器件层变薄而减小。 最佳活性层厚度平衡两种效果。 AlGaInP LED包括基板和包括第一导电类型的AlGaInP下约束层，第二导电类型的AlGaInP有源区和第二导电类型的AlGaInP上约束层的器件层。 有源区的吸光度是发光器件中总吸光度的至少五分之一。 该装置可选地包括至少一个插入限制层和活性区域中的一个AlGaInP的后置层。 可以用氧掺杂p型上约束层提高可靠性。

    III-nitride light-emitting devices with improved high-current efficiency
    2.
    发明授权
    III-nitride light-emitting devices with improved high-current efficiency 有权
    具有改善的高电流效率的III族氮化物发光器件

    公开(公告)号：US06943381B2

    公开(公告)日：2005-09-13

    申请号：US10769590

    申请日：2004-01-30

    申请人： Nathan F. Gardner ,  Christopher P. Kocot ,  Stephen A. Stockman

    发明人： Nathan F. Gardner ,  Christopher P. Kocot ,  Stephen A. Stockman

    IPC分类号： H01L33/00 ,  H01L33/32

    CPC分类号： H01L33/32

    摘要： A light-emitting semiconductor device comprises a III-Nitride active region and a III-Nitride layer formed proximate to the active region and having a thickness that exceeds a critical thickness for relaxation of strain in the III-Nitride layer. The III-Nitride layer may be a carrier confinement layer, for example. In another aspect of the invention, a light-emitting semiconductor device comprises a III-Nitride light emitting layer, an InxAlyGa1-x-yN (0≦x≦1, 0≦y≦1, x+y≦1), and a spacer layer interposing the light emitting layer and the InxAlyGa1-x-yN layer. The spacer layer may advantageously space the InxAlyGa1-x-yN layer and any contaminants therein apart from the light emitting layer. The composition of the III-Nitride layer may be advantageously selected to determine a strength of an electric field in the III-Nitride layer and thereby increase the efficiency with which the device emits light.

    摘要翻译： 发光半导体器件包括在有源区附近形成的III-氮化物有源区和III-氮化物层，其厚度超过III-氮化物层中的应变松弛的临界厚度。 例如，III-氮化物层可以是载流子限制层。 在本发明的另一方面中，一种发光半导体器件包括III族氮化物发光层，In-Al 2 O 3，Ga 1-xy， SUB> N（0 <= x <= 1,0,0 <= y <= 1，x + y <= 1），以及插入发光层和In < 1＆lt; 1＆gt; Ga 1-xy N层。 间隔层可以有利地将In和/或Al 2 Y 1 Ga 1-x-y N N层及其中的任何污染物与发光层隔开。 可以有利地选择III-氮化物层的组成以确定III-氮化物层中的电场的强度，从而提高器件发光的效率。

    Halide dopant process for producing semi-insulating group III-V regions for semiconductor devices
    5.
    发明授权
    Halide dopant process for producing semi-insulating group III-V regions for semiconductor devices 失效
    用于半导体器件制造半绝缘组III-V区的卤化物掺杂剂工艺

    公开(公告)号：US5656538A

    公开(公告)日：1997-08-12

    申请号：US410782

    申请日：1995-03-24

    申请人： Nathan F. Gardner ,  Stephen A. Stockman ,  Quesnell J. Hartmann ,  Gregory E. Stillman

    发明人： Nathan F. Gardner ,  Stephen A. Stockman ,  Quesnell J. Hartmann ,  Gregory E. Stillman

    IPC分类号： H01L21/205 ,  H01L21/20

    CPC分类号： H01L21/02392 ,  H01L21/02461 ,  H01L21/02543 ,  H01L21/02573 ,  H01L21/0262 ,  Y10S148/003 ,  Y10S148/064 ,  Y10S438/918

    摘要： A process for growing semi-insulating layers of indium phosphide and other group III-V materials through the use of halide dopant or etchant introduction during growth. Gas phase epitaxial growth techniques are utilized at low temperatures to produce indium phosphide layers having a resistivity greater than approximately 10.sup.7 ohm-cm. According to the preferred embodiment carbon tetrachloride is used as a dopant at flow rates above 5 sccm to grow the layers with substrate growth temperatures ranging from approximately 460.degree. C. to 525.degree. C. This temperature range provides an advantage over the transition metal techniques for doping indium phosphide since the high temperatures generally required for those techniques limit the ability to control growth. Good surface morphology is also obtained through the growth according to the present invention. The process may be used to form many types of group III-V semiconductor devices.

    摘要翻译： 在生长期间通过使用卤素掺杂剂或蚀刻剂引入生长磷化铟和其它III-V族材料的半绝缘层的方法。 在低温下使用气相外延生长技术产生电阻率大于约107欧姆 - 厘米的磷化铟层。 根据优选的实施方案，四氯化碳以5sccm以上的流速用作掺杂剂，以生长基底生长温度为约460℃至525℃的层。该温度范围优于过渡金属技术 掺杂磷化铟，因为这些技术通常需要的高温限制了控制生长的能力。 通过根据本发明的生长也可获得良好的表面形态。 该方法可用于形成许多类型的III-V族III族半导体器件。

    Methods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including same
    9.
    发明授权
    Methods of forming relaxed layers of semiconductor materials, semiconductor structures, devices and engineered substrates including same 有权
    形成半导体材料的弛豫层，半导体结构，器件和包括其的工程衬底的方法

    公开(公告)号：US08486771B2

    公开(公告)日：2013-07-16

    申请号：US12563953

    申请日：2009-09-21

    申请人： Fabrice Letertre ,  Bruce Faure ,  Michael R. Krames ,  Nathan F. Gardner

    发明人： Fabrice Letertre ,  Bruce Faure ,  Michael R. Krames ,  Nathan F. Gardner

    IPC分类号： H01L21/00

    CPC分类号： H01L21/02639 ,  H01L21/02367 ,  H01L21/02389 ,  H01L21/02458 ,  H01L21/0254

    摘要： Methods of fabricating relaxed layers of semiconductor materials include forming structures of a semiconductor material overlying a layer of a compliant material, and subsequently altering a viscosity of the compliant material to reduce strain within the semiconductor material. The compliant material may be reflowed during deposition of a second layer of semiconductor material. The compliant material may be selected so that, as the second layer of semiconductor material is deposited, a viscosity of the compliant material is altered imparting relaxation of the structures. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Methods of fabricating semiconductor structures and devices are also disclosed. Novel intermediate structures are formed during such methods. Engineered substrates include a plurality of structures comprising a semiconductor material disposed on a layer of material exhibiting a changeable viscosity.

    摘要翻译： 制造半导体材料的松弛层的方法包括形成覆盖柔性材料层的半导体材料的结构，随后改变柔性材料的粘度以减小半导体材料内的应变。 在沉积第二层半导体材料期间，柔性材料可以回流。 可以选择柔性材料，使得当沉积第二层半导体材料时，改变柔性材料的粘度赋予结构松弛性。 在一些实施例中，半导体材料层可以包括III-V型半导体材料，例如氮化铟镓。 还公开了制造半导体结构和器件的方法。 在这种方法中形成了新的中间结构。 工程衬底包括多个结构，其包括设置在表现出可变粘度的材料层上的半导体材料。