公开(公告)号：US20170218512A1

公开(公告)日：2017-08-03

申请号：US15013091

申请日：2016-02-02

Applicant: National Cheng Kung University ,  Delta Electronics Inc.

Inventor： Wen-Hsi Lee ,  Hsin-Chang Tsai

IPC: C23C16/442

CPC classification number: C23C16/442 ,  B22F1/00 ,  B22F1/0055 ,  B22F1/025 ,  B22F2998/10 ,  B22F2999/00 ,  B22F1/0088 ,  B22F2001/0092 ,  B22F9/24 ,  B22F3/1007 ,  B22F2201/50

Abstract: A thick-film copper paste is made. A displacement reaction with low cost is used to precipitate nano-silver (Ag) to be grown on copper particles. Thus, the thick-film copper paste is made of the copper powder coated with nano-Ag. The paste can be sintered in the air and is increased in overall electrical conductivity. The copper inside is not oxidized. Its resistance on electromigration is good. Furthermore, the paste can be added with frit as a sintering aid to assist sintering the nano-Ag-coated copper paste. Furthermore, even in a high-temperature heat treatment, the powder of nano-Ag-coated copper is still antioxidant and can replace the silver paste used in the current market.

公开(公告)号：US10424508B2

公开(公告)日：2019-09-24

申请号：US14748811

申请日：2015-06-24

Applicant: Delta Electronics, Inc.

Inventor： Hsin-Chang Tsai ,  Peng-Hsin Lee

IPC: H01L21/768 ,  H01L21/288 ,  H01L23/495 ,  H01L23/48 ,  H01L23/00 ,  H01L25/07 ,  H01L25/18 ,  H01L25/00 ,  H01L21/268

Abstract: A method of forming an interconnection structure is disclosed, including providing a substrate having a first side and a second side opposite to the first side, forming a via hole through the substrate, wherein the via hole has a first opening in the first side and a second opening in the second side, forming a first pad covering the first opening, and forming a via structure in the via hole subsequent to forming the first pad, wherein the via structure includes a conductive material and is adjoined to the first pad.

公开(公告)号：US09385070B2

公开(公告)日：2016-07-05

申请号：US13930817

申请日：2013-06-28

Applicant: DELTA ELECTRONICS, INC.

Inventor： Hsin-Chang Tsai ,  Chia-Yen Lee ,  Peng-Hsin Lee

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L23/538 ,  H01L23/495 ,  H01L25/18 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/495 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49527 ,  H01L23/49531 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/5221 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L25/18 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37124 ,  H01L2224/37139 ,  H01L2224/37144 ,  H01L2224/37147 ,  H01L2224/37155 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73221 ,  H01L2224/73255 ,  H01L2924/00014 ,  H01L2924/13063 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/84

Abstract: A semiconductor component comprising a lateral semiconductor device, a vertical semiconductor device, and a leadframe is provided. The lateral semiconductor device has a first side and a second side, and a first electrode, a second electrode, and a control electrode positioned on the first side. The vertical semiconductor device has a first side and a second side, a second electrode and a control electrode of it positioned on the second side and a first electrode of it positioned on the first side. The leadframe electrically and respectively connected to each of the first electrode of the lateral semiconductor device, the second electrode of the lateral semiconductor device, the second electrode of the vertical semiconductor device, and the control electrodes, wherein the first side of the vertical semiconductor device is mounted on the second side of the lateral semiconductor device, and the first electrodes of both devices are electrically connected.

Abstract translation: 提供包括横向半导体器件，垂直半导体器件和引线框架的半导体元件。 横向半导体器件具有第一侧和第二侧，以及位于第一侧上的第一电极，第二电极和控制电极。 垂直半导体器件具有位于第二侧上的第一侧和第二侧，第二电极和控制电极以及位于第一侧的第一电极。 引线框电连接并分别连接到横向半导体器件的第一电极，横向半导体器件的第二电极，垂直半导体器件的第二电极和控制电极，其中垂直半导体器件的第一侧 安装在横向半导体器件的第二侧上，并且两个器件的第一电极电连接。

公开(公告)号：US10892210B2

公开(公告)日：2021-01-12

申请号：US15283963

申请日：2016-10-03

Applicant: Delta Electronics, Inc.

Inventor： Hsin-Chang Tsai ,  Peng-Hsin Lee

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: A package structure is provided. The package structure includes a leadframe including a plurality of connection portions; a device including a substrate, an active layer disposed on the substrate and a plurality of electrodes disposed on the active layer, wherein the electrodes of the device are connected to the connection portions of the leadframe; a conductive unit having a first side and a second side, wherein the first side of the conductive unit connects to the substrate of the device and the conductive unit connects to at least one of the connection portions of the leadframe; and an encapsulation material covering the device and the leadframe, wherein the second side of the conductive unit is exposed from the encapsulation material.

公开(公告)号：US10741644B2

公开(公告)日：2020-08-11

申请号：US15358469

申请日：2016-11-22

Applicant: Delta Electronics, Inc.

Inventor： Shiau-Shi Lin ,  Tzu-Hsuan Cheng ,  Hsin-Chang Tsai

IPC: H01L29/08 ,  H01L23/522 ,  H01L29/66 ,  H01L23/367 ,  H01L23/31

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; an active layer disposed on the substrate; a via through the active layer; and a plurality of electrodes disposed on the active layer and into the via. Additionally, a package structure that includes the semiconductor device is also provided. The electrode is electrically connected to the substrate through the via.

公开(公告)号：US09905439B2

公开(公告)日：2018-02-27

申请号：US15142458

申请日：2016-04-29

Applicant: Delta Electronics, Inc.

Inventor： Hsin-Chang Tsai ,  Chia-Yen Lee ,  Peng-Hsin Lee

IPC: H01L21/48 ,  H01L23/498 ,  B32B37/12

CPC classification number: H01L21/4857 ,  B32B37/12 ,  B32B2307/202 ,  H01L21/4839 ,  H01L21/486 ,  H01L23/49503 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/49861 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00014

Abstract: A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.

公开(公告)号：US09847312B2

公开(公告)日：2017-12-19

申请号：US15157896

申请日：2016-05-18

Applicant: DELTA ELECTRONICS, INC.

Inventor： Hsin-Chang Tsai ,  Peng-Hsin Lee

IPC: H01L29/15 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L24/33 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13091

Abstract: A package structure includes an encapsulant, an active component, a first lead frame segment, and a second lead frame segment. The active component is encapsulated within the encapsulant and includes first and second electrodes. The first and second electrodes are respectively disposed on and electrically connected to the first and second lead frame segments. The first and second lead frame segments respectively have first and second exposed surfaces. The first exposed surface and the first electrode are respectively located on opposite sides of the first lead frame segment. The second exposed surface and the second electrode are respectively located on opposite sides of the second lead frame segment. The first and second exposed surfaces are exposed outside the encapsulant. A minimal distance from the first electrode to the second electrode is less than a minimal distance from the first exposed surface to the second exposed surface.

公开(公告)号：US09159699B2

公开(公告)日：2015-10-13

申请号：US13675297

申请日：2012-11-13

Applicant: DELTA ELECTRONICS, INC.

Inventor： Hsin-Chang Tsai ,  Chia-Yen Lee ,  Peng-Hisn Lee

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/07 ,  H01L25/18 ,  H01L25/00 ,  H01L23/495

CPC classification number: H01L21/76898 ,  H01L21/268 ,  H01L21/2885 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76895 ,  H01L23/481 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/91 ,  H01L25/074 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0332 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05147 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/73221 ,  H01L2224/73255 ,  H01L2224/73257 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/13064 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An interconnection structure is provided having a substrate with at least one electric device formed adjacent to a first side of the substrate and a via hole formed therethrough. The via hole has a first opening adjacent to the first side of the substrate. A via structure is disposed in the via hole without exceeding the first opening. A first pad is disposed on the first side of the substrate and covers the via hole. A second pad is disposed on a second side of the substrate opposite to the first side, wherein the via structure extends into the second pad. The first pad is adjoined to the via structure and electrically connects with the at least one electric device, and the first pad has a protrusion portion extending into the via hole.

Abstract translation: 提供一种互连结构，具有具有邻近基板的第一侧形成的至少一个电气装置的基板和穿过其形成的通孔。 通孔具有与基板的第一侧相邻的第一开口。 通孔结构设置在通孔中而不超过第一开口。 第一焊盘设置在衬底的第一侧上并覆盖通孔。 第二衬垫设置在与第一侧相对的衬底的第二侧上，其中通孔结构延伸到第二衬垫中。 第一焊盘邻接于通孔结构并与至少一个电气设备电连接，并且第一焊盘具有延伸到通孔中的突出部分。

公开(公告)号：US10685904B2

公开(公告)日：2020-06-16

申请号：US14549996

申请日：2014-11-21

Applicant: DELTA ELECTRONICS, INC.

Inventor： Hsin-Chang Tsai ,  Chia-Yen Lee ,  Peng-Hsin Lee

IPC: H01L23/433 ,  H01L23/31

Abstract: A packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode.

公开(公告)号：US09865531B2

公开(公告)日：2018-01-09

申请号：US15142588

申请日：2016-04-29

Applicant: Delta Electronics, Inc.

Inventor： Hsin-Chang Tsai ,  Chia-Yen Lee ,  Peng-Hsin Lee

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49575 ,  H01L21/4839 ,  H01L23/49503 ,  H01L23/49531 ,  H01L23/49541 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49111 ,  H01L2924/01007 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/13064

Abstract: A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer disposed on the metal carrier and partially covering the metal carrier, and a patterned conductive layer disposed on the patterned insulation layer. The first chip is disposed on the metal carrier not covered by the patterned insulation layer. The second chip is disposed on the patterned conductive layer and electrically connected to the first chip.