公开(公告)号：US08217516B2

公开(公告)日：2012-07-10

申请号：US12477178

申请日：2009-06-03

申请人： Nobuaki Takahashi ,  Masahiro Komuro ,  Satoshi Matsui

发明人： Nobuaki Takahashi ,  Masahiro Komuro ,  Satoshi Matsui

IPC分类号： H01L23/24

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/13009 ,  H01L2224/131 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/17181 ,  H01L2924/00014

摘要： In this semiconductor device, the through-hole is formed in the substrate, and is located under the conductive pattern. The insulating layer is located at the bottom surface of the through-hole. The conductive pattern is located on one surface side of the substrate. The opening pattern is formed in the insulating layer which is located between the through-hole and the conductive pattern, where the distance r3 from the circumference of the opening pattern to the central axis of the through-hole is smaller than the distance r1 in the through-hole. By providing the opening pattern, the conductive pattern is exposed at the bottom surface of the through-hole. The bump is located on the back surface side of the substrate, and is formed integrally with the through-electrode.

摘要翻译： 在该半导体装置中，通孔形成在基板上，位于导电图案的下方。 绝缘层位于通孔的底面。 导电图案位于基板的一个表面侧。 开口图案形成在位于通孔和导电图案之间的绝缘层中，其中从开口图案的周边到通孔的中心轴线的距离r3小于通孔中的距离r1 通孔。 通过设置开口图案，导电图案在通孔的底面露出。 凸块位于基板的背面侧，与贯通电极一体形成。

公开(公告)号：US20070126085A1

公开(公告)日：2007-06-07

申请号：US11602346

申请日：2006-11-21

申请人： Masaya Kawano ,  Koji Soejima ,  Nobuaki Takahashi ,  Yoichiro Kurita ,  Masahiro Komuro ,  Satoshi Matsui

发明人： Masaya Kawano ,  Koji Soejima ,  Nobuaki Takahashi ,  Yoichiro Kurita ,  Masahiro Komuro ,  Satoshi Matsui

IPC分类号： H01L23/48 ,  H01L21/58

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/562 ,  H01L23/642 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2223/6622 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10155 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device includes an interconnect member, a first semiconductor chip, a second semiconductor chip, a resin layer, an inorganic insulating layer, and a through electrode. The first semiconductor chip is mounted in a face-down manner on the interconnect member. The resin layer covers the side surface of the first semiconductor chip. This inorganic insulating layer is in contact with the back surface of the first semiconductor chip, and directly covers the back surface. Also, the inorganic insulating layer extends over the resin layer. The through electrode penetrates the inorganic insulating layer and the semiconductor substrate of the first semiconductor chip. The second semiconductor chip is mounted in a face-down manner on the inorganic insulating layer that covers the back surface of the first semiconductor chip in the uppermost layer.

摘要翻译： 半导体器件包括互连部件，第一半导体芯片，第二半导体芯片，树脂层，无机绝缘层和贯通电极。 第一半导体芯片以面朝下的方式安装在互连构件上。 树脂层覆盖第一半导体芯片的侧表面。 该无机绝缘层与第一半导体芯片的背面接触，直接覆盖背面。 此外，无机绝缘层在树脂层上延伸。 贯通电极穿透第一半导体芯片的无机绝缘层和半导体衬底。 第二半导体芯片以面朝下的方式安装在覆盖最上层的第一半导体芯片的背面的无机绝缘层上。

公开(公告)号：US20090302430A1

公开(公告)日：2009-12-10

申请号：US12477178

申请日：2009-06-03

申请人： Nobuaki Takahashi ,  Masahiro Komuro ,  Satoshi Matsui

发明人： Nobuaki Takahashi ,  Masahiro Komuro ,  Satoshi Matsui

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L21/3205

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/13009 ,  H01L2224/131 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/17181 ,  H01L2924/00014

摘要： In this semiconductor device, the through-hole is formed in the substrate, and is located under the conductive pattern. The insulating layer is located at the bottom surface of the through-hole. The conductive pattern is located on one surface side of the substrate. The opening pattern is formed in the insulating layer which is located between the through-hole and the conductive pattern, where the distance r3 from the circumference of the opening pattern to the central axis of the through-hole is smaller than the distance r1 in the through-hole. By providing the opening pattern, the conductive pattern is exposed at the bottom surface of the through-hole. The bump is located on the back surface side of the substrate, and is formed integrally with the through-electrode.

摘要翻译： 在该半导体装置中，通孔形成在基板上，位于导电图案的下方。 绝缘层位于通孔的底面。 导电图案位于基板的一个表面侧。 开口图案形成在位于通孔和导电图案之间的绝缘层中，其中从开口图案的周边到通孔的中心轴线的距离r3小于通孔中的距离r1 通孔。 通过设置开口图案，导电图案在通孔的底面露出。 凸块位于基板的背面侧，与贯通电极一体形成。

公开(公告)号：US08791567B2

公开(公告)日：2014-07-29

申请号：US13494537

申请日：2012-06-12

申请人： Nobuaki Takahashi ,  Masahiro Komuro ,  Satoshi Matsui

发明人： Nobuaki Takahashi ,  Masahiro Komuro ,  Satoshi Matsui

IPC分类号： H01L23/48

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05684 ,  H01L2224/13009 ,  H01L2224/131 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/17181 ,  H01L2924/00014

摘要： In this semiconductor device, the through-hole is formed in the substrate, and is located under the conductive pattern. The insulating layer is located at the bottom surface of the through-hole. The conductive pattern is located on one surface side of the substrate. The opening pattern is formed in the insulating layer which is located between the through-hole and the conductive pattern, where the distance r3 from the circumference of the opening pattern to the central axis of the through-hole is smaller than the distance r1 in the through-hole. By providing the opening pattern, the conductive pattern is exposed at the bottom surface of the through-hole. The bump is located on the back surface side of the substrate, and is formed integrally with the through-electrode.

摘要翻译： 在该半导体装置中，通孔形成在基板上，位于导电图案的下方。 绝缘层位于通孔的底面。 导电图案位于基板的一个表面侧。 开口图案形成在位于通孔和导电图案之间的绝缘层中，其中从开口图案的周边到通孔的中心轴线的距离r3小于通孔中的距离r1 通孔。 通过设置开口图案，导电图案在通孔的底面露出。 凸块位于基板的背面侧，与贯通电极一体形成。

公开(公告)号：US08395269B2

公开(公告)日：2013-03-12

申请号：US12656616

申请日：2010-02-04

申请人： Masaya Kawano ,  Koji Soejima ,  Nobuaki Takahashi ,  Yoichiro Kurita ,  Masahiro Komuro ,  Satoshi Matsui

发明人： Masaya Kawano ,  Koji Soejima ,  Nobuaki Takahashi ,  Yoichiro Kurita ,  Masahiro Komuro ,  Satoshi Matsui

IPC分类号： H01L21/50

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/562 ,  H01L23/642 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2223/6622 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10155 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacturing a semiconductor device includes forming an interconnect member, mounting a first semiconductor chip having a semiconductor substrate in a face-down manner on the interconnect member, forming a resin layer on the interconnect member to cover a side surface of the first semiconductor chip, thinning the first semiconductor chip and the resin layer, forming an inorganic insulating layer on a back surface of the first semiconductor chip so as to be in contact with the back surface and to extend over the resin layer, and forming a through electrode so as to penetrate the inorganic insulating layer and the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法包括形成互连部件，将具有半导体衬底的第一半导体芯片以面向下的方式安装在互连部件上，在互连部件上形成树脂层以覆盖第一半导体的侧表面 芯片，使第一半导体芯片和树脂层变薄，在第一半导体芯片的背面上形成无机绝缘层，以与背面接触并延伸到树脂层上，并形成通孔，从而形成通孔 以穿透无机绝缘层和半导体衬底。

公开(公告)号：US08102049B2

公开(公告)日：2012-01-24

申请号：US11842973

申请日：2007-08-22

申请人： Nobuaki Takahashi ,  Masahiro Komuro ,  Koji Soejima ,  Satoshi Matsui ,  Masaya Kawano

发明人： Nobuaki Takahashi ,  Masahiro Komuro ,  Koji Soejima ,  Satoshi Matsui ,  Masaya Kawano

IPC分类号： H01L23/52

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/06181 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11901 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/00014

摘要： The present invention provides a semiconductor device including at least one of an insulating layer and a semiconductor layer each including a hole formed therein, and a through electrode provided in the hole. In the semiconductor device, the side wall of the hole is constituted of a first region from the opening of the hole to a predetermined position between the opening of the hole and the bottom surface of the hole, and a second region from the predetermined position to the bottom surface of the hole. The through electrode includes a seed layer and a plating layer. The seed layer covers the second region and the bottom surface of the hole without covering the first region. In addition, the plating layer covers the seed layer and at least a part of the first region.

摘要翻译： 本发明提供一种半导体器件，其包括绝缘层和各自包括形成在其中的孔的半导体层中的至少一个，以及设置在孔中的通孔。 在半导体装置中，孔的侧壁由从孔的开口到孔的开口部与孔的底面之间的规定位置的第一区域和从规定位置到第二区域 孔的底面。 通孔包括种子层和镀层。 种子层覆盖孔的第二区域和底部表面而不覆盖第一区域。 此外，电镀层覆盖种子层和第一区域的至少一部分。

公开(公告)号：US20100144091A1

公开(公告)日：2010-06-10

申请号：US12656616

申请日：2010-02-04

申请人： Masaya Kawano ,  Koji Soejima ,  Nobuaki Takahashi ,  Yoichiro Kurita ,  Masahiro Komuro ,  Satoshi Matsui

发明人： Masaya Kawano ,  Koji Soejima ,  Nobuaki Takahashi ,  Yoichiro Kurita ,  Masahiro Komuro ,  Satoshi Matsui

IPC分类号： H01L21/50

CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/562 ,  H01L23/642 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2223/6622 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10155 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of manufacturing a semiconductor device includes forming an interconnect member, mounting a first semiconductor chip having a semiconductor substrate in a face-down manner on the interconnect member, forming a resin layer on the interconnect member to cover a side surface of the first semiconductor chip, thinning the first semiconductor chip and the resin layer, forming an inorganic insulating layer on a back surface of the first semiconductor chip so as to be in contact with the back surface and to extend over the resin layer, and forming a through electrode so as to penetrate the inorganic insulating layer and the semiconductor substrate.

摘要翻译： 一种制造半导体器件的方法包括形成互连部件，将具有半导体衬底的第一半导体芯片以面向下的方式安装在互连部件上，在互连部件上形成树脂层以覆盖第一半导体的侧表面 芯片，使第一半导体芯片和树脂层变薄，在第一半导体芯片的背面上形成无机绝缘层，以与背面接触并延伸到树脂层上，并形成通孔，从而形成通孔 以穿透无机绝缘层和半导体衬底。

公开(公告)号：US08426311B2

公开(公告)日：2013-04-23

申请号：US12801458

申请日：2010-06-09

申请人： Nobuaki Takahashi ,  Masahiro Komuro

发明人： Nobuaki Takahashi ,  Masahiro Komuro

IPC分类号： H01L21/445

CPC分类号： C23C18/1651 ,  C23C18/1632 ,  C23C18/32 ,  C23C18/54 ,  H01L21/288 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device includes forming a laminated structure of a plurality of metal films on a semiconductor substrate using an electroless plating method. The forming of the metal films includes: performing an electroless plating process including a reduction reaction using a first plating tank; and performing an electroless plating process by only a substitution reaction using a second plating tank. The electroless plating process including the reduction reaction that is performed using the first plating tank is performed in a shading environment, and the electroless plating process performed by only the substitution reaction using the second plating tank is performed in a non-shading environment.

摘要翻译： 一种半导体器件的制造方法包括使用无电镀法在半导体衬底上形成多个金属膜的叠层结构。 金属膜的形成包括：使用第一镀槽进行包括还原反应的无电镀处理; 并且仅使用第二镀槽进行取代反应进行化学镀处理。 包括使用第一镀槽进行的还原反应的化学镀处理在遮蔽环境中进行，并且在非遮蔽环境中进行仅使用第二镀槽的取代反应进行的化学镀处理。

公开(公告)号：US20110027987A1

公开(公告)日：2011-02-03

申请号：US12801458

申请日：2010-06-09

申请人： Nobuaki Takahashi ,  Masahiro Komuro

发明人： Nobuaki Takahashi ,  Masahiro Komuro

IPC分类号： H01L21/445

CPC分类号： C23C18/1651 ,  C23C18/1632 ,  C23C18/32 ,  C23C18/54 ,  H01L21/288 ,  H01L21/76898 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05556 ,  H01L2224/05644 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

摘要： A method for manufacturing a semiconductor device includes forming a laminated structure of a plurality of metal films on a semiconductor substrate using an electroless plating method. The forming of the metal films includes: performing an electroless plating process including a reduction reaction using a first plating tank; and performing an electroless plating process by only a substitution reaction using a second plating tank. The electroless plating process including the reduction reaction that is performed using the first plating tank is performed in a shading environment, and the electroless plating process performed by only the substitution reaction using the second plating tank is performed in a non-shading environment.

摘要翻译： 一种半导体器件的制造方法包括使用无电镀法在半导体衬底上形成多个金属膜的叠层结构。 金属膜的形成包括：使用第一镀槽进行包括还原反应的无电镀处理; 并且仅使用第二镀槽进行取代反应进行化学镀处理。 包括使用第一镀槽进行的还原反应的化学镀处理在遮蔽环境中进行，并且在非遮蔽环境中进行仅使用第二镀槽的取代反应进行的化学镀处理。

公开(公告)号：US09758594B2

公开(公告)日：2017-09-12

申请号：US12989600

申请日：2009-04-27

申请人： Nobuaki Takahashi

发明人： Nobuaki Takahashi

IPC分类号： C07K16/28 ,  C07K16/00 ,  C07K16/46 ,  A61K39/395

CPC分类号： C07K16/468 ,  A61K39/39591 ,  C07K16/2818 ,  C07K16/2878 ,  C07K2317/51 ,  C07K2317/56 ,  C07K2317/622 ,  C07K2317/624 ,  C07K2317/626 ,  C07K2317/64 ,  C07K2319/00

摘要： The present invention relates to a multivalent antibody comprising multiple heavy chain variable regions of antibody linked to each other via a linker comprising an amino acid sequence encoding an immunoglobulin domain or a fragment thereof.