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公开(公告)号：US07786589B2
公开(公告)日：2010-08-31
申请号：US11951559
申请日：2007-12-06
IPC分类号： H01L23/52
CPC分类号： H01L23/53295 , H01L21/7682 , H01L21/76831 , H01L21/76835 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： In one aspect of the present invention, a semiconductor device may include a semiconductor substrate having a semiconductor element on an upper surface, a first dielectric film provided on the semiconductor substrate, a second dielectric film provided on the first dielectric film, a metal ring provided in the first dielectric film and the second dielectric film and configured to form a closed loop in a plan view, a first region surrounded by the metal ring in a plan view, a second region provided outside of the metal ring in a plan view, a plurality of via contacts provided in the first dielectric film in the first and second region, a plurality of wirings provided in the second dielectric film in the first and second region, and an air gap provided in the second dielectric film in the first region.
摘要翻译： 在本发明的一个方面中，半导体器件可以包括在上表面具有半导体元件的半导体衬底，设置在半导体衬底上的第一电介质膜，设置在第一绝缘膜上的第二电介质膜，设置有金属环 在第一电介质膜和第二电介质膜中，构造成在平面图中形成闭环，在平面图中由金属环包围的第一区域，平面图中设置在金属环外侧的第二区域， 设置在第一和第二区域中的第一电介质膜中的多个通孔触点，设置在第一和第二区域中的第二电介质膜中的多个布线以及设置在第一区域中的第二电介质膜中的气隙。
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公开(公告)号：US20080296775A1
公开(公告)日：2008-12-04
申请号：US11951559
申请日：2007-12-06
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/53295 , H01L21/7682 , H01L21/76831 , H01L21/76835 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： In one aspect of the present invention, a semiconductor device may include a semiconductor substrate having a semiconductor element on an upper surface, a first dielectric film provided on the semiconductor substrate, a second dielectric film provided on the first dielectric film, a metal ring provided in the first dielectric film and the second dielectric film and configured to form a closed loop in a plan view, a first region surrounded by the metal ring in a plan view, a second region provided outside of the metal ring in a plan view, a plurality of via contacts provided in the first dielectric film in the first and second region, a plurality of wirings provided in the second dielectric film in the first and second region, and an air gap provided in the second dielectric film in the first region.
摘要翻译： 在本发明的一个方面中，半导体器件可以包括在上表面具有半导体元件的半导体衬底，设置在半导体衬底上的第一电介质膜，设置在第一绝缘膜上的第二电介质膜，设置有金属环 在第一电介质膜和第二电介质膜中，构造成在平面图中形成闭环，在平面图中由金属环包围的第一区域，平面图中设置在金属环外侧的第二区域， 设置在第一和第二区域中的第一电介质膜中的多个通孔触点，设置在第一和第二区域中的第二电介质膜中的多个布线以及设置在第一区域中的第二电介质膜中的气隙。
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公开(公告)号：US06781236B2
公开(公告)日：2004-08-24
申请号：US10052259
申请日：2002-01-23
IPC分类号： H01L2312
CPC分类号： H01P3/088 , H01L23/5222 , H01L23/528 , H01L2223/6627 , H01L2223/6638 , H01L2924/0002 , H01L2924/1903 , H01L2924/3011 , H01L2924/00
摘要： This invention includes a signal line 17, through which a signal having a desired frequency f0 passes, formed on a semiconductor substrate 10, and a differential signal line 13 through which a signal in opposite phase to the signal passing through the signal line passes, or which is connected to a ground power supply, the signal line and the differential signal line are formed so as to be substantially in parallel with each other via an insulating layer 15, and an actual wiring length l of the signal line is longer than a wiring length l0 determined by the following equation l 0 = L C + R 2 + 8 π 2 f 0 2 L 2 4 π 2 f 0 2 C 2 R 2 + 4 π 2 f 0 2 L 2 where R represents a resistance component, L represents an inductance component, and C represents a capacitance component, per unit length of the signal line when no differential signal line exists.
摘要翻译： 本发明包括形成在半导体衬底10上的具有期望频率f0的信号通过的信号线17和与通过信号线的信号相反相位的信号通过的差分信号线13，或 连接到接地电源，信号线和差分信号线经由绝缘层15形成为基本上彼此平行，并且信号线的实际布线长度l比布线长 长度l0由下式确定，其中R表示电阻分量，L表示电感分量，C表示当不存在差分信号线时信号线的每单位长度的电容分量。
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4.发明授权公开(公告)号：US06750138B2
公开(公告)日：2004-06-15
申请号：US10407426
申请日：2003-04-07
IPC分类号： H01L214763
CPC分类号： H01L24/05 , H01L23/5222 , H01L23/5329 , H01L24/03 , H01L2224/05556 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01078 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： A plurality of wiring layers are laminated on an LSI chip. Each wiring layer includes an electrode to which is applied a mechanical pressure, a first insulating film formed in a region where it is necessary to have a high mechanical strength and having the electrode formed therein, a second insulating film formed in the same layer as the layer of the first insulating film and formed in a region where a mechanical strength higher than that of the first insulating layer is not required, and a wiring layer formed on the surface of the second insulating film.
摘要翻译： 多个布线层层压在LSI芯片上。 每个布线层包括施加有机械压力的电极，形成在需要具有高机械强度且其中形成有电极的区域中的第一绝缘膜，形成在与第一绝缘膜相同的层中的第二绝缘膜 形成在不需要比第一绝缘层高的机械强度的区域中的第一绝缘膜的层，以及形成在第二绝缘膜的表面上的布线层。
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5.发明授权公开(公告)号：US06563218B2
公开(公告)日：2003-05-13
申请号：US09995602
申请日：2001-11-29
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L23/5222 , H01L23/5329 , H01L24/03 , H01L2224/05556 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01078 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： A plurality of wiring layers are laminated on an LSI chip. Each wiring layer includes an electrode to which is applied a mechanical pressure, a first insulating film formed in a region where it is necessary to have a high mechanical strength and having the electrode formed therein, a second insulating film formed in the same layer as the layer of the first insulating film and formed in a region where a mechanical strength higher than that of the first insulating layer is not required, and a wiring layer formed on the surface of the second insulating film.
摘要翻译： 多个布线层层压在LSI芯片上。 每个布线层包括施加有机械压力的电极，形成在需要具有高机械强度且其中形成有电极的区域中的第一绝缘膜，形成在与第一绝缘膜相同的层中的第二绝缘膜 形成在不需要比第一绝缘层高的机械强度的区域中的第一绝缘膜的层，以及形成在第二绝缘膜的表面上的布线层。
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公开(公告)号：US06534870B1
公开(公告)日：2003-03-18
申请号：US09594843
申请日：2000-06-15
申请人： Yoshiaki Shimooka , Noriaki Matsunaga , Hideki Shibata , Rempei Nakata , Hideshi Miyajima , Motonobu Kawai
发明人： Yoshiaki Shimooka , Noriaki Matsunaga , Hideki Shibata , Rempei Nakata , Hideshi Miyajima , Motonobu Kawai
IPC分类号： H01L23485
CPC分类号： H01L23/53223 , H01L23/5226 , H01L23/53214 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Al wirings of first to fifth layers are formed on a P—SiO2 film, and FSG films are formed between the wiring layers. An organic silicon oxide film is formed between wirings in one same wiring layer. The Al wirings in the first and second layers have a carbon concentration of 22 wt %, and the Al wirings in the third to fifth layers have a carbon concentration of 20 wt %.
摘要翻译： 在P-SiO 2膜上形成第一至第五层的Al布线，并且在布线层之间形成FSG膜。 在一个相同的布线层中的布线之间形成有机氧化硅膜。 第一层和第二层的Al配线的碳浓度为22重量％，第三至第五层的Al配线的碳浓度为20重量％。
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公开(公告)号：US07691740B2
公开(公告)日：2010-04-06
申请号：US12250772
申请日：2008-10-14
IPC分类号： H01L21/4763
CPC分类号： H01L21/02115 , H01L21/0337 , H01L21/3105 , H01L21/31144 , H01L21/31633 , H01L21/76801 , H01L21/76808 , H01L21/76822 , H01L21/76826 , H01L21/76832 , H01L21/76835
摘要： The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench.
摘要翻译： 根据本发明的半导体器件制造方法，在半导体衬底上形成含有碳的层间电介质膜，在层间电介质膜的与表面接近的部分形成保护膜，其中碳浓度低 通过选择性地去除层间电介质膜和保护膜的期望区域形成沟槽，使得该区域从保护膜的表面延伸到层间电介质膜的底表面，将碳供应到层间电介质 膜和保护膜，并且通过在沟槽中埋入导电材料形成导电层。
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公开(公告)号：US07339256B2
公开(公告)日：2008-03-04
申请号：US10974922
申请日：2004-10-28
IPC分类号： H01L29/72
CPC分类号： H01L23/564 , H01L23/522 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a first insulating layer provided above a semiconductor substrate. The first insulating layer includes a layer consisting essentially of a material having a relative dielectric constant smaller than 3. The first insulating layer includes a first integral structure consisting of a plug and wiring. The upper surface of the wiring is flush with the upper surface of the first insulating layer, and the lower surface of the plug is flush with the lower surface of the first insulating layer. A region protective member is formed of a second integral structure consisting of a plug and wiring. The second integral structure extends from the upper surface of the first insulating layer to the lower surface of the first insulating layer. The region protective member surrounds one of first to n-th regions (n being a natural 2 or more) partitioned by a boundary region on a horizontal plane.
摘要翻译： 半导体器件包括设置在半导体衬底之上的第一绝缘层。 第一绝缘层包括基本上由相对介电常数小于3的材料组成的层。第一绝缘层包括由插头和布线组成的第一整体结构。 布线的上表面与第一绝缘层的上表面齐平，插头的下表面与第一绝缘层的下表面齐平。 区域保护构件由由插头和布线组成的第二整体结构形成。 第二整体结构从第一绝缘层的上表面延伸到第一绝缘层的下表面。 区域保护构件围绕由水平面上的边界区划分的第一至第n区域（n为自然2以上）中的一个。
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公开(公告)号：US20090042358A1
公开(公告)日：2009-02-12
申请号：US12250772
申请日：2008-10-14
IPC分类号： H01L21/76
CPC分类号： H01L21/02115 , H01L21/0337 , H01L21/3105 , H01L21/31144 , H01L21/31633 , H01L21/76801 , H01L21/76808 , H01L21/76822 , H01L21/76826 , H01L21/76832 , H01L21/76835
摘要： The semiconductor device fabrication method according the present invention having, forming an interlayer dielectric film containing carbon above a semiconductor substrate, forming a protective film on that portion of the interlayer dielectric film, which is close to the surface and in which the carbon concentration is low, forming a trench by selectively removing a desired region of the interlayer dielectric film and protective film, such that the region extends from the surface of the protective film to the bottom surface of the interlayer dielectric film, supplying carbon to the interface between the interlayer dielectric film and protective film, and forming a conductive layer by burying a conductive material in the trench.
摘要翻译： 根据本发明的半导体器件制造方法，在半导体衬底上形成含有碳的层间电介质膜，在层间电介质膜的与表面接近的部分形成保护膜，其中碳浓度低 通过选择性地去除层间电介质膜和保护膜的期望区域形成沟槽，使得该区域从保护膜的表面延伸到层间电介质膜的底表面，将碳供应到层间电介质 膜和保护膜，并且通过在沟槽中埋入导电材料形成导电层。
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公开(公告)号：US06291891B1
公开(公告)日：2001-09-18
申请号：US09228642
申请日：1999-01-12
申请人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko , Hideki Shibata , Naofumi Nakamura , Minakshisundaran Balasubramanian Anand , Tadashi Matsuno , Katsuya Okumura
发明人： Kazuyuki Higashi , Noriaki Matsunaga , Akihiro Kajita , Tetsuo Matsuda , Tadashi Iijima , Hisashi Kaneko , Hideki Shibata , Naofumi Nakamura , Minakshisundaran Balasubramanian Anand , Tadashi Matsuno , Katsuya Okumura
IPC分类号： H01L2348
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/76807 , H01L21/76814 , H01L21/76819 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76844 , H01L21/76849 , H01L21/76885 , H01L21/76897 , H01L23/5226 , H01L2221/1026 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.
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