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    Semiconductor device
    1.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08431991B2

    公开(公告)日：2013-04-30

    申请号：US12265728

    申请日：2008-11-05

    申请人： Noriyuki Iwamuro

    发明人： Noriyuki Iwamuro

    IPC分类号： H01L29/24 ,  H01L20/78

    CPC分类号： H01L29/7811 ,  H01L29/0623 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

    摘要： A semiconductor device includes a peripheral voltage withstanding structure, which includes an n− SiC layer, an n SiC layer and a p SiC layer are provided successively on an n+ SiC layer. A trench is formed in the peripheral voltage withstanding structure portion so that the trench passes through the p SiC layer 15 and the n SiC layer 14 and reaches the n− SiC layer. This trench is wider than a trench having a trench gate structure in the active region portion. A p+ SiC region is provided along a bottom of the trench so as to be located under the trench. A sidewall and the bottom of the trench are covered with an oxide film and an insulating film having a total thickness not smaller than 1.1 μm. The oxide film and insulating film absorb a large part of a voltage applied between a source and a drain.

    摘要翻译： 在n + SiC层上连续设置包括n型SiC层，n SiC层和p SiC层的外围耐压结构的半导体装置。 在外围耐压结构部分形成沟槽，使得沟槽通过p SiC层15和n SiC层14到达n-SiC层。 该沟槽比在有源区域部分中具有沟槽栅极结构的沟槽更宽。 沿着沟槽的底部提供p + SiC区域，以便位于沟槽下方。 沟槽的侧壁和底部被氧化物膜和总厚度不小于1.1μm的绝缘膜覆盖。 氧化膜和绝缘膜吸收施加在源极和漏极之间的电压的大部分。

    Insulated gate thyristor
    4.
    发明授权
    Insulated gate thyristor 失效
    绝缘栅极晶闸管

    公开(公告)号：US5914503A

    公开(公告)日：1999-06-22

    申请号：US798743

    申请日：1997-02-13

    申请人： Noriyuki Iwamuro ,  Yuichi Harada

    发明人： Noriyuki Iwamuro ,  Yuichi Harada

    IPC分类号： H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111

    CPC分类号： H01L29/749 ,  H01L29/7455

    摘要： An insulated gate thyristor is provided in which an inversion layer is created beneath a gate electrode to which a voltage is applied. An emitter region of a first conductivity type is biased to the same potential as a first main electrode via a MOSFET channel, and a thyristor portion consisting of the emitter region, a second base region of a second conductivity type, a base layer of the first conductivity type and an emitter layer of the second conductivity type is turned on. As electrons are injected uniformly from the entire emitter region, the insulated gate thyristor quickly shifts to the thyristor mode, and the on-voltage of the insulated gate thyristor of the invention is lowered. The insulated gate thyristor of the invention does not require a hole current that flows through the second base region of a convention EST in the Z-direction. In turning off, the pn junction recovers quickly without causing current localization, and the breakdown withstand capability if improved.

    摘要翻译： 提供一种绝缘栅极晶闸管，其中在施加电压的栅电极下面形成反型层。 第一导电类型的发射极区域经由MOSFET沟道被偏置到与第一主电极相同的电位，并且由发射极区域，第二导电类型的第二基极区域，第一导电类型的基极层 导电类型和第二导电类型的发射极层导通。 由于电子从整个发射极区均匀注入，所以绝缘栅极晶闸管迅速转移到晶闸管模式，并且本发明的绝缘栅晶闸管的导通电压降低。 本发明的绝缘栅极晶闸管不需要在常规EST的Z方向上流过第二基极区域的空穴电流。 在关闭时，pn结快速恢复，而不会导致电流定位，如果改进，击穿耐受能力。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08299522B2

    公开(公告)日：2012-10-30

    申请号：US13049463

    申请日：2011-03-16

    申请人： Noriyuki Iwamuro

    发明人： Noriyuki Iwamuro

    IPC分类号： H01L29/66

    CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/66734 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813

    摘要： A super-junction semiconductor substrate is configured in such a manner that an n-type semiconductor layer of a parallel pn structure is opposed to a boundary region between an active area and a peripheral breakdown-resistant structure area. A high-concentration region is formed at the center between p-type semiconductor layers that are located on both sides of the above n-type semiconductor layer. A region where a source electrode is in contact with a channel layer is formed over the n-type semiconductor layer. A portion where the high-concentration region is in contact with the channel layer functions as a diode. The breakdown voltage of the diode is set lower than that of the device.

    摘要翻译： 以这样的方式配置超结半导体衬底，使得并联pn结构的n型半导体层与有源区和外围抗击结构区之间的边界区域相对。 在位于上述n型半导体层的两侧的p型半导体层之间的中心处形成高浓度区域。 在n型半导体层上形成有源极与沟道层接触的区域。 高浓度区域与沟道层接触的部分用作二极管。 二极管的击穿电压设置为低于器件的击穿电压。

    P-channel silicon carbide MOSFET
    6.
    发明授权
    P-channel silicon carbide MOSFET 有权
    P沟道碳化硅MOSFET

    公开(公告)号：US08198676B2

    公开(公告)日：2012-06-12

    申请号：US12717670

    申请日：2010-03-04

    申请人： Noriyuki Iwamuro

    发明人： Noriyuki Iwamuro

    IPC分类号： H01L27/108 ,  H01L29/76

    CPC分类号： H01L29/7813 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7806

    摘要： A second trench in each source electrode portion (Schottky diode portion) is formed to have a depth equal to or larger than the depth of a first trench in each gate electrode portion. The distance between the first and second trenches is set to be not longer than 10 μm. A source electrode is formed in the second trench and a Schottky junction is formed in the bottom portion of the second trench. In this manner, it is possible to provide a wide band gap semiconductor device which is small-sized, which has low on-resistance and low loss characteristic, in which electric field concentration into a gate insulating film is relaxed to suppress reduction of a withstand voltage, and which has high avalanche breakdown tolerance at turn-off time.

    摘要翻译： 每个源电极部分（肖特基二极管部分）中的第二沟槽被形成为具有等于或大于每个栅电极部分中的第一沟槽的深度的深度。 第一沟槽和第二沟槽之间的距离设定为不大于10μm。 在第二沟槽中形成源电极，在第二沟槽的底部形成肖特基结。 以这种方式，可以提供一种小型的宽带隙半导体器件，其具有低导通电阻和低损耗特性，其中放电到栅极绝缘膜中的电场浓度以抑制耐受的降低 电压，并且在关断时间具有高雪崩击穿容限。

    Manufacturing method of a semiconductor device
    7.
    发明授权
    Manufacturing method of a semiconductor device 失效
    半导体器件的制造方法

    公开(公告)号：US07713794B2

    公开(公告)日：2010-05-11

    申请号：US12262970

    申请日：2008-10-31

    申请人： Noriyuki Iwamuro

    发明人： Noriyuki Iwamuro

    IPC分类号： H01L21/332

    CPC分类号： H01L29/7802 ,  H01L21/31116 ,  H01L22/26 ,  H01L29/0657 ,  H01L29/0834 ,  H01L29/0886 ,  H01L29/41741 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/861

    摘要： A manufacturing method of a semiconductor device includes the steps of forming an insulating film having a prescribed repetition pattern on one surface of a semiconductor substrate and then depositing semiconductor layers on the one surface of the semiconductor substrate; forming trenches from the other surface of the semiconductor substrate in such a manner that the trenches come into contact with the semiconductor layer, that plural trenches are formed for each semiconductor chip to be formed on the semiconductor substrate, and that at least one pattern of the insulating film is exposed through the bottom of each trench; and covering the inside surfaces of the trenches and the other surface of the semiconductor substrate with a metal electrode.

    摘要翻译： 半导体器件的制造方法包括以下步骤：在半导体衬底的一个表面上形成具有规定的重复图案的绝缘膜，然后在半导体衬底的一个表面上沉积半导体层; 以使沟槽与半导体层接触的方式从半导体衬底的另一个表面形成沟槽，为在半导体衬底上形成的每个半导体芯片形成多个沟槽，并且至少一个图案 绝缘膜通过每个沟槽的底部暴露; 并用金属电极覆盖沟槽的内表面和半导体衬底的另一表面。

    WIDE BAND GAP SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
    8.
    发明申请
    WIDE BAND GAP SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME 有权
    宽带隙半导体器件及其制造方法

    公开(公告)号：US20090283776A1

    公开(公告)日：2009-11-19

    申请号：US12426169

    申请日：2009-04-17

    申请人： Noriyuki Iwamuro

    发明人： Noriyuki Iwamuro

    IPC分类号： H01L29/20 ,  H01L29/24 ,  H01L21/28

    CPC分类号： H01L29/7827 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/452 ,  H01L29/47 ,  H01L29/475 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7839

    摘要： A wide band gap semiconductor device is disclosed. A first trench in a gate electrode part and a second trench in a source electrode part (Schottky diode part) are disposed so that the first and second trenches are close to each other while and the second trench is deeper than the first trench. A metal electrode is formed in the second trench to form a Schottky junction on a surface of an n-type drift layer in the bottom of the second trench. Further, a p+-type region is provided in part of the built-in Schottky diode part being in contact with the surface of the n-type drift layer, preferably in the bottom of the second trench. The result is a wide band gap semiconductor device which is small in size and low in on-resistance and loss, and in which electric field concentration applied on a gate insulating film is relaxed to suppress lowering of withstand voltage to thereby increase avalanche breakdown tolerance at turning-off time.

    摘要翻译： 公开了一种宽带隙半导体器件。 栅电极部分中的第一沟槽和源电极部分（肖特基二极管部分）中的第二沟槽被设置为使得第一沟槽和第二沟槽彼此靠近而第二沟槽比第一沟槽更深。 金属电极形成在第二沟槽中，以在第二沟槽的底部的n型漂移层的表面上形成肖特基结。 此外，在内置肖特基二极管部分的一部分中，优选在第二沟槽的底部与n型漂移层的表面接触，提供p +型区域。 结果是尺寸小，导通电阻和损耗低的宽带隙半导体器件，并且其中施加在栅极绝缘膜上的电场浓度被放宽以抑制耐受电压的降低，从而增加雪崩击穿耐受性 关闭时间。

    Insulated gate thyristor
    9.
    发明授权
    Insulated gate thyristor 失效
    绝缘栅极晶闸管

    公开(公告)号：US5684306A

    公开(公告)日：1997-11-04

    申请号：US626334

    申请日：1996-04-02

    申请人： Noriyuki Iwamuro

    发明人： Noriyuki Iwamuro

    IPC分类号： H01L29/744 ,  H01L29/739 ,  H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L29/78 ,  H01L31/111

    CPC分类号： H01L29/7455 ,  H01L29/7412 ,  H01L29/749 ,  H01L29/0696

    摘要： An insulated gate thyristor is provided which includes a first-conductivity-type base layer having a high resistivity, a first and a second second-conductivity-type base region separately formed in a surface layer of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, and a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region. A gate electrode is formed through an insulating film on exposed portions of the first second-conductivity-type base region, the first-conductivity-type base layer, and the second second-conductivity-type base region, which exposed portions are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region. A first main electrode is held in contact with both the first second-conductivity-type base region and the first-conductivity-type source region. A first-conductivity-type semiconductor film is interposed between and held in contact with the first main electrode and an exposed portion of the second second-conductivity-type base region, to cooperate with the second second-conductivity-type base region to form a diode. A second-conductivity-type emitter layer is formed on the other surface of the first-conductivity-type base layer, and a second main electrode is held in contact with the second-conductivity-type emitter layer.

    摘要翻译： 提供一种绝缘栅极晶闸管，其包括具有高电阻率的第一导电型基极层，分别形成在第一导电型基极层的表面层中的第一和第二第二导电型基极区域， 形成在第一第二导电型基极区域的表面层中的第一导电型源极区域和形成在第二第二导电型基极区域的表面层中的第一导电型发射极区域。 在第一第二导电型基极区域，第一导电型基极层和第二第二导电型基极区域的露出部分上通过绝缘膜形成栅极电极， 第一导电型源极区域和第一导电型发射极区域。 第一主电极与第一第二导电型基极区域和第一导电型源极区域保持接触。 第一导电型半导体膜介于第一主电极和第二第二导电型基区的露出部分之间并与之保持接触，以与第二第二导电型基极区域配合形成 二极管。 第二导电型发射极层形成在第一导电型基极层的另一个表面上，第二主电极与第二导电型发射极层保持接触。