公开(公告)号：US20130040454A1

公开(公告)日：2013-02-14

申请号：US13205063

申请日：2011-08-08

申请人： Cyril Cabral, JR. ,  Gregory M. Fritz ,  Christian Lavoie ,  Conal E. Murray ,  Kenneth P. Rodbell

发明人： Cyril Cabral, JR. ,  Gregory M. Fritz ,  Christian Lavoie ,  Conal E. Murray ,  Kenneth P. Rodbell

IPC分类号： H01L21/28 ,  H01L21/304 ,  H01L21/302

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76828 ,  H01L21/76886 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203

摘要： A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected proximity to an interconnect, igniting the reactive material layer, and annealing the interconnect via heat transferred from the ignited reactive material layer. The method can also be implemented in connection with a silicide/silicon interface as well as a zone of silicon-based technology.

摘要翻译： 提供了一种通过退火工艺改性硅基技术的化学或微结构的方法。 该方法包括将反应性材料层沉积在选定的互连附近，点燃反应性材料层，以及通过从点燃的反应性材料层传递的热量使互连件退火。 该方法还可以结合硅化物/硅界面以及硅基技术的区域来实现。

公开(公告)号：US20110127438A1

公开(公告)日：2011-06-02

申请号：US12627076

申请日：2009-11-30

申请人： Cyril Cabral, JR. ,  Michael S. Gordon ,  Steven J. Koester ,  Conal E. Murray ,  Kenneth P. Rodbell ,  Stephen M. Rossnagel ,  Robert L. Wisnieff ,  Jeng-bang Yau

发明人： Cyril Cabral, JR. ,  Michael S. Gordon ,  Steven J. Koester ,  Conal E. Murray ,  Kenneth P. Rodbell ,  Stephen M. Rossnagel ,  Robert L. Wisnieff ,  Jeng-bang Yau

IPC分类号： G01T1/02 ,  G01T3/00

CPC分类号： G01T1/026

摘要： A system for determining an amount of radiation includes a dosimeter configured to receive the amount of radiation, the dosimeter comprising a circuit having a resonant frequency, such that the resonant frequency of the circuit changes according to the amount of radiation received by the dosimeter, the dosimeter further configured to absorb RF energy at the resonant frequency of the circuit; a radio frequency (RF) transmitter configured to transmit the RF energy at the resonant frequency to the dosimeter; and a receiver configured to determine the resonant frequency of the dosimeter based on the absorbed RF energy, wherein the amount of radiation is determined based on the resonant frequency.

摘要翻译： 用于确定辐射量的系统包括配置成接收辐射量的剂量计，该剂量计包括具有谐振频率的电路，使得电路的谐振频率根据剂量计接收的辐射量而改变， 剂量计还被配置为吸收电路的谐振频率处的RF能量; 射频（RF）发射器，被配置为以共振频率将所述RF能量传输到所述剂量计; 以及接收器，被配置为基于所吸收的RF能量来确定所述剂量计的谐振频率，其中所述辐射量基于所述谐振频率来确定。

公开(公告)号：US20130001784A1

公开(公告)日：2013-01-03

申请号：US13611363

申请日：2012-09-12

申请人： Cyril Cabral, JR. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

发明人： Cyril Cabral, JR. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

IPC分类号： H01L23/48

CPC分类号： H01L21/28518 ,  H01L21/76841 ,  H01L23/53238 ,  H01L31/022408 ,  H01L31/022425 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

摘要： A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.

摘要翻译： 具有接触结构的半导体器件或光电池，其包括硅（Si）衬底; 沉积在硅衬底上的金属合金层; 金属硅化物层和由金属合金层热退火同时形成的扩散层; 以及沉积在金属硅化物和阻挡层上的金属层。

公开(公告)号：US20110309508A1

公开(公告)日：2011-12-22

申请号：US12819634

申请日：2010-06-21

申请人： Cyril Cabral, JR. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

发明人： Cyril Cabral, JR. ,  John M. Cotte ,  Kathryn C. Fisher ,  Laura L. Kosbar ,  Christian Lavoie ,  Zhu Liu ,  Kenneth P. Rodbell ,  Xiaoyan Shao

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L21/28518 ,  H01L21/76841 ,  H01L23/53238 ,  H01L31/022408 ,  H01L31/022425 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/00

摘要： A semiconductor device or a photovoltaic cell having a contact structure, which includes a silicon (Si) substrate; a metal alloy layer deposited on the silicon substrate; a metal silicide layer and a diffusion layer formed simultaneously from thermal annealing the metal alloy layer; and a metal layer deposited on the metal silicide and barrier layers.

摘要翻译： 具有接触结构的半导体器件或光电池，其包括硅（Si）衬底; 沉积在硅衬底上的金属合金层; 金属硅化物层和由金属合金层热退火同时形成的扩散层; 以及沉积在金属硅化物和阻挡层上的金属层。

公开(公告)号：US20090315182A1

公开(公告)日：2009-12-24

申请号：US12145163

申请日：2008-06-24

申请人： Paul R. Besser ,  Christian Lavoie ,  Cyril Cabral, JR. ,  Stephen M. Rossnagel ,  Kenneth P. Rodbell

发明人： Paul R. Besser ,  Christian Lavoie ,  Cyril Cabral, JR. ,  Stephen M. Rossnagel ,  Kenneth P. Rodbell

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/76889 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming an interconnect structure includes forming a dielectric layer above a first layer having a conductive region defined therein. An opening is defined in the dielectric layer to expose at least a portion of the conductive region. A metal silicide is formed in the opening to define the interconnect structure. A semiconductor device includes a first layer having a conductive region defined therein, a dielectric layer formed above the first layer, and a metal silicide interconnect structure extending through the dielectric layer to communicate with the conductive region.

摘要翻译： 形成互连结构的方法包括在其中限定有导电区域的第一层之上形成介电层。 在电介质层中限定开口以暴露导电区域的至少一部分。 在开口中形成金属硅化物以限定互连结构。 半导体器件包括其中限定有导电区域的第一层，形成在第一层之上的电介质层和延伸穿过介电层以与导电区域连通的金属硅化物互连结构。

公开(公告)号：US20130062769A1

公开(公告)日：2013-03-14

申请号：US13232085

申请日：2011-09-14

申请人： Cyril Cabral, JR. ,  Takeshi Nogami ,  Jeffrey P. Gambino ,  Qiang Huang ,  Kenneth P. Rodbell

发明人： Cyril Cabral, JR. ,  Takeshi Nogami ,  Jeffrey P. Gambino ,  Qiang Huang ,  Kenneth P. Rodbell

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L21/7684 ,  H01L21/2885 ,  H01L21/76841 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect structure and a method of manufacturing the metal interconnect structure. Manganese (Mn) is incorporated into a copper (Cu) interconnect structure in order to modify the microstructure to achieve bamboo-style grain boundaries in sub-90 nm technologies. Preferably, bamboo grains are separated at distances less than the “Blech” length so that copper (Cu) diffusion through grain boundaries is avoided. The added Mn also triggers the growth of Cu grains down to the bottom surface of the metal line so that a true bamboo microstructure reaching to the bottom surface is formed and the Cu diffusion mechanism along grain boundaries oriented along the length of the metal line is eliminated.

摘要翻译： 金属互连结构和金属互连结构的制造方法。 锰（Mn）被掺入到铜（Cu）互连结构中，以便在90nm以下的技术中改变微观结构以实现竹型晶界。 优选地，竹颗粒在小于Blech长度的距离处分离，使得避免通过晶界的铜（Cu）扩散。 添加的Mn还触发Cu颗粒向金属线底部的生长，从而形成达到底面的真正的竹结构，消除沿着金属线长度取向的晶界的Cu扩散机理 。

公开(公告)号：US20090243053A1

公开(公告)日：2009-10-01

申请号：US12483364

申请日：2009-06-12

申请人： Cyril Cabral, JR. ,  Michael S. Gordon ,  Kenneth P. Rodbell

发明人： Cyril Cabral, JR. ,  Michael S. Gordon ,  Kenneth P. Rodbell

IPC分类号： H01L23/556

CPC分类号： H01L23/556 ,  H01L21/76801 ,  H01L21/76834 ,  H01L21/76838 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05006 ,  H01L2224/05554 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01084 ,  H01L2924/01092 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15312 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05552

摘要： A structure for reduction of soft error rates in integrated circuits. The structure including: a semiconductor substrate; and a stack of one or more wiring levels stacked from a lowermost wiring level to an uppermost wiring level, the lowermost wiring level nearer the semiconductor substrate than the uppermost wiring level; and an alpha particle blocking layer on a top surface of the uppermost wiring level of the one or more wiring levels, the blocking layer comprising metal wires and a dielectric material, the blocking layer having a combination of a thickness of the blocking layer and a volume percent of metal wires in the blocking layer sufficient to stop a predetermined percentage of alpha particles of a selected energy or less striking the blocking layer from penetrating into the stack of one or more wiring levels or the substrate.

摘要翻译： 用于降低集成电路中软错误率的结构。 该结构包括：半导体衬底; 以及从最下布线电平堆叠到最上布线电平的一个或多个布线电平的堆叠，比最上布线电平更靠近半导体基板的最下布线电平; 以及在所述一个或多个布线层的最上布线层的顶表面上的α粒子阻挡层，所述阻挡层包括金属线和介电材料，所述阻挡层具有阻挡层的厚度和体积 阻挡层中的金属线的百分比足以阻止预定百分比的选定能量的α粒子或更少的击穿阻挡层的金属线穿透到一个或多个布线层或衬底的堆叠中。

公开(公告)号：US20120267768A1

公开(公告)日：2012-10-25

申请号：US13533182

申请日：2012-06-26

申请人： Paul Stephen Andry ,  Cyril Cabral, JR. ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

发明人： Paul Stephen Andry ,  Cyril Cabral, JR. ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

IPC分类号： H01L23/556 ,  B23K3/00

CPC分类号： H01L23/556 ,  H01L21/304 ,  H01L21/481 ,  H01L24/11 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29111 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/2064 ,  H01L2924/3025 ,  H01L2224/13111 ,  H01L2924/00014

摘要： A structure and system for forming the structure. The structure includes a semiconductor chip and an interposing shield having a top side and a bottom side. The semiconductor chip includes N chip electric pads, wherein N is a positive integer of at least 2. The N chip electric pads are electrically connected to a plurality of devices on the semiconductor chip. The electric shield includes 2N electric conductors and N shield electric pads. Each shield electrical pad is in electrical contact and direct physical contact with a corresponding pair of electric conductors of the 2N electric conductors. The interposing shield includes a shield material. The shield material includes a first semiconductor material. The semiconductor chip is bonded to the top side of the interposing shield. Each chip electric pads is in electrical contact and direct physical contact with a corresponding shield electrical pad of the N shield electric pads.

摘要翻译： 用于形成结构的结构和系统。 该结构包括半导体芯片和具有顶侧和底侧的插入屏蔽。 半导体芯片包括N个芯片电极焊盘，其中N是至少为2的正整数。N个芯片电极焊盘与半导体芯片上的多个器件电连接。 电气屏蔽包括2N个导电体和N个屏蔽电极垫。 每个屏蔽电焊垫与2N电导体的相应电导体电接触并直接物理接触。 中间屏蔽包括屏蔽材料。 屏蔽材料包括第一半导体材料。 半导体芯片被结合到插入式屏蔽的顶侧。 每个芯片电焊盘与N个屏蔽电焊盘的相应屏蔽电焊垫电接触并直接物理接触。

公开(公告)号：US20100323517A1

公开(公告)日：2010-12-23

申请号：US12869113

申请日：2010-08-26

申请人： Brett C. Baker-O'Neal ,  Cyril Cabral, JR. ,  Qiang Huang ,  Kenneth P. Rodbell

发明人： Brett C. Baker-O'Neal ,  Cyril Cabral, JR. ,  Qiang Huang ,  Kenneth P. Rodbell

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/76873 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Cobalt is added to a copper seed layer, a copper plating layer, or a copper capping layer in order to modify the microstructure of copper lines and vias. The cobalt can be in the form of a copper-cobalt alloy or as a very thin cobalt layer. The grain boundaries configured in bamboo microstructure in the inventive metal interconnect structure shut down copper grain boundary diffusion. The composition of the metal interconnect structure after grain growth contains from about 1 ppm to about 10% of cobalt in atomic concentration. Grain boundaries extend from a top surface of a copper-cobalt alloy line to a bottom surface of the copper-cobalt alloy line, and are separated from any other grain boundary by a distance greater than a width of the copper-cobalt alloy line.

摘要翻译： 为了改变铜线和通孔的微观结构，将钴添加到铜种子层，铜镀层或铜覆盖层。 钴可以是铜 - 钴合金的形式或作为非常薄的钴层。 本发明金属互连结构中竹结构中晶界的结构关闭了铜晶界扩散。 晶粒生长后的金属互连结构的组成含有约1ppm至约10原子浓度的钴。 晶粒边界从铜 - 钴合金线的顶表面延伸到铜 - 钴合金线的底表面，并且与任何其它晶界分开大于铜 - 钴合金线的宽度的距离。

公开(公告)号：US20080318365A1

公开(公告)日：2008-12-25

申请号：US12200352

申请日：2008-08-28

申请人： Paul Stephen Andry ,  Cyril Cabral, JR. ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

发明人： Paul Stephen Andry ,  Cyril Cabral, JR. ,  Kenneth P. Rodbell ,  Robert L. Wisnieff

IPC分类号： H01L21/60

CPC分类号： H01L23/556 ,  H01L21/304 ,  H01L21/481 ,  H01L24/11 ,  H01L24/29 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29111 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/2064 ,  H01L2924/3025 ,  H01L2224/13111 ,  H01L2924/00014

摘要： A structure fabrication method. First, an integrated circuit including N chip electric pads is provided electrically connected to a plurality of devices on the integrated circuit. Then, an interposing shield having a top side and a bottom side and having N electric conductors in the interposing shield is provided being exposed to a surrounding ambient at the top side but not at the bottom side. Next, the integrated circuit is bonded to the top side of the interposing shield such that the N chip electric pads are in electrical contact with the N electric conductors. Next, the bottom side of the interposing shield is polished so as to expose the N electric conductors to the surrounding ambient at the bottom side of the interposing shield. Then, N solder bumps are formed on the polished bottom side of the interposing shield and in electrical contact with the N electric conductors.

摘要翻译： 一种结构制造方法。 首先，将包括N个芯片电焊盘的集成电路电连接到集成电路上的多个器件。 然后，设置具有顶侧和底侧并且在插入式屏蔽中具有N个电导体的插入式屏蔽件，其暴露于顶侧周围的环境而不是在底侧。 接下来，集成电路接合到中间屏蔽的顶侧，使得N个芯片电极焊盘与N个导电体电接触。 接下来，对中介屏蔽的底面进行抛光，以将N根电导体暴露于插入式屏蔽的底侧周围环境。 然后，在中间屏蔽的抛光底面上形成N个焊料凸块，并与N个导电体电接触。