公开(公告)号：US20050215056A1

公开(公告)日：2005-09-29

申请号：US10811758

申请日：2004-03-29

申请人： Patrick Morrow ,  R. List ,  Michael Chan

发明人： Patrick Morrow ,  R. List ,  Michael Chan

IPC分类号： H01L21/18 ,  H01L21/302 ,  H01L21/304 ,  H01L21/762

CPC分类号： H01L21/304 ,  H01L21/187 ,  Y10S438/977

摘要： According to one embodiment a method is disclosed. The method includes applying a photoresist layer to a first wafer, etching the first wafer, bonding the first wafer to a second wafer and thinning the first wafer; wherein an unsupported bevel portion of the first wafer is removed.

摘要翻译： 根据一个实施例，公开了一种方法。 该方法包括将光致抗蚀剂层施加到第一晶片，蚀刻第一晶片，将第一晶片接合到第二晶片并使第一晶片变薄; 其中去除第一晶片的未支撑的斜面部分。

公开(公告)号：US20050059217A1

公开(公告)日：2005-03-17

申请号：US10665824

申请日：2003-09-17

申请人： Patrick Morrow ,  R. List ,  Sarah Kim

发明人： Patrick Morrow ,  R. List ,  Sarah Kim

IPC分类号： H01L21/768 ,  H01L21/98 ,  H01L23/48 ,  H01L25/065 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/8182 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/01082

摘要： Various methods of forming backside connections on a wafer stack are disclosed. To form the backside connections, vias are formed in a first wafer that is to be bonded with a second wafer. The vias used for the backside connections are formed on a side of the first wafer along with an interconnect structure, and the backside connections are formed on an opposing side of the first wafer using these vias.

摘要翻译： 公开了在晶片叠层上形成背面连接的各种方法。 为了形成背面连接，通孔形成在要与第二晶片结合的第一晶片中。 用于背面连接的通路与互连结构一起形成在第一晶片的一侧，并且使用这些通孔在第一晶片的相对侧上形成背面连接。

公开(公告)号：US20050164490A1

公开(公告)日：2005-07-28

申请号：US11071434

申请日：2005-03-02

申请人： Patrick Morrow ,  R. List ,  Sarah Kim

发明人： Patrick Morrow ,  R. List ,  Sarah Kim

IPC分类号： H01L21/768 ,  H01L21/98 ,  H01L23/48 ,  H01L25/065 ,  H01L21/4763

CPC分类号： H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/2919 ,  H01L2224/8182 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01079 ,  H01L2924/00014 ,  H01L2924/01082

摘要： Various methods of forming backside connections on a wafer stack are disclosed. To form the backside connections, vias are formed in a first wafer that is to be bonded with a second wafer. The vias used for the backside connections are formed on a side of the first wafer along with an interconnect structure, and the backside connections are formed on an opposing side of the first wafer using these vias.

公开(公告)号：US20070278668A1

公开(公告)日：2007-12-06

申请号：US11893198

申请日：2007-08-15

申请人： Sarah Kim ,  R. List ,  James Maveety ,  Alan Myers ,  Quat Vu

发明人： Sarah Kim ,  R. List ,  James Maveety ,  Alan Myers ,  Quat Vu

IPC分类号： H01L23/34

CPC分类号： H01L23/473 ,  H01L23/34 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2224/82

摘要： An integrated electroosmotic pump may be incorporated in the same integrated circuit package with a re-combiner, and an integrated circuit chip to be cooled by fluid pumped by the electroosmotic pump.

公开(公告)号：US20060097383A1

公开(公告)日：2006-05-11

申请号：US11298280

申请日：2005-12-09

申请人： Shriram Ramanathan ,  Sarah Kim ,  R. List ,  Gregory Chrysler

发明人： Shriram Ramanathan ,  Sarah Kim ,  R. List ,  Gregory Chrysler

IPC分类号： H01L23/34 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L35/32 ,  H01L23/38 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L27/16 ,  H01L2224/05001 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81801 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/4554

摘要： A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.

公开(公告)号：US20050077619A1

公开(公告)日：2005-04-14

申请号：US10682137

申请日：2003-10-08

申请人： Shriram Ramanathan ,  Sarah Kim ,  R. List ,  Gregory Chrysler

发明人： Shriram Ramanathan ,  Sarah Kim ,  R. List ,  Gregory Chrysler

IPC分类号： H01L21/60 ,  H01L23/38 ,  H01L23/485 ,  H01L23/50 ,  H01L27/16 ,  H01L35/32 ,  H01L23/34 ,  H01L21/44

CPC分类号： H01L35/32 ,  H01L23/38 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L27/16 ,  H01L2224/05001 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48471 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81801 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01015 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/4554

摘要： A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.

摘要翻译： 提供了一种微电子组件，其具有形成在模具上的热电元件，以便当电流流过热电元件时将热量从模具中排出。 在一个实施例中，热电元件集成在管芯的有源侧上的导电互连元件之间。 在另一实施例中，热电元件位于管芯的背面，并与管芯前侧的载体基板电连接。 在另一个实施例中，热电元件形成在二次基板上并转移到管芯上。

公开(公告)号：US20050112816A1

公开(公告)日：2005-05-26

申请号：US10721441

申请日：2003-11-24

申请人： Alan Myers ,  Sarah Kim ,  R. List

发明人： Alan Myers ,  Sarah Kim ,  R. List

IPC分类号： H01L23/473 ,  H01L21/8238

CPC分类号： H01L23/473 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/00

摘要： A device where the electrodes of an electroosmotic pump are located directly in the flow-producing region of the electroosmotic pump is described as well as methods of forming such a device. Placing the electrodes of an electroosmotic pump directly in the flow-producing region of the electroosmotic pump may increase the flow rate of a cooling fluid that is pumped through the pump. The cooling fluid may then remove a greater amount of heat from the substrate over which it is flowed. The substrate may be the non-device side of a die or a thermal management chip that is placed in direct contact with the non-device side of a die. In these instances the electroosmotic pump may be part of a microelectronic package containing the die or the thermal management chip.

摘要翻译： 描述电渗泵的电极直接位于电渗泵的流动产生区域中的装置以及形成这种装置的方法。 将电渗泵的电极直接放置在电渗泵的流动产生区域中可以增加泵送通过泵的冷却流体的流量。 然后，冷却流体可以从其流过的基底上移除更大量的热量。 衬底可以是与管芯的非器件侧直接接触的管芯或热管理芯片的非器件侧。 在这些情况下，电渗泵可以是包含管芯或热管理芯片的微电子封装的一部分。

公开(公告)号：US20050095751A1

公开(公告)日：2005-05-05

申请号：US10984604

申请日：2004-11-08

申请人： Stefan Hau-Riege ,  R. List

发明人： Stefan Hau-Riege ,  R. List

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/44 ,  H01L21/48

CPC分类号： H01L21/76843 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76849 ,  H01L21/76864 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making a semiconductor device is described. That method comprises forming a conductive layer that contacts a via, such that the conductive layer includes a higher concentration of an electromigration retarding amount of a dopant near the via than away from the via.

摘要翻译： 描述制造半导体器件的方法。 该方法包括形成接触通孔的导电层，使得导电层在远离通孔的地方包括较高浓度的通孔附近的掺杂剂的电迁移量。

公开(公告)号：US20070111386A1

公开(公告)日：2007-05-17

申请号：US11603521

申请日：2006-11-21

申请人： Sarah Kim ,  R. List ,  Scot Kellar

发明人： Sarah Kim ,  R. List ,  Scot Kellar

IPC分类号： H01L21/00

CPC分类号： H01L21/76831 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76898 ,  H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/8083 ,  H01L2224/80895 ,  H01L2224/81894 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2224/05552 ,  H01L2224/81 ,  H01L2224/83

摘要： A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.

公开(公告)号：US20060076678A1

公开(公告)日：2006-04-13

申请号：US11281709

申请日：2005-11-16

申请人： Sarah Kim ,  Bob Martell ,  David Ayers ,  R. List ,  Peter Moon ,  Steven Towle ,  Anna George

发明人： Sarah Kim ,  Bob Martell ,  David Ayers ,  R. List ,  Peter Moon ,  Steven Towle ,  Anna George

IPC分类号： H01L23/48

CPC分类号： H01L24/12 ,  H01L21/76838 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53238 ,  H01L24/11 ,  H01L24/16 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05666 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00014

摘要： A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.

摘要翻译： 在芯片或晶片级的受控崩溃芯片连接（C 4）凸起处制造具有一个或多个厚金属层的互连结构的工艺流程。 互连结构可以用在微处理器的后端互连中。 一个或多个集成的厚金属层可以改善功率传递并且降低在管芯/封装接口处的管芯的机械应力。