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公开(公告)号：US06395579B2
公开(公告)日：2002-05-28
申请号：US09789892
申请日：2001-02-21
申请人： Patrick W. Tandy , Joseph M. Brand , Brad D. Rumsey , Steven R. Stephenson , David J. Corisis , Todd O. Bolken , Edward A. Schrock , Brenton L. Dickey
发明人： Patrick W. Tandy , Joseph M. Brand , Brad D. Rumsey , Steven R. Stephenson , David J. Corisis , Todd O. Bolken , Edward A. Schrock , Brenton L. Dickey
IPC分类号： H01L2144
CPC分类号： H01L23/3107 , H01L21/565 , H01L23/3157 , H01L23/4985 , H01L24/48 , H01L2224/05599 , H01L2224/4824 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.
摘要翻译： 集成电路封装可以部分地形成有封装区域。 可以通过提供在封装区域和关键部件所在的区域之间收集密封剂流出物的空腔来防止密封剂在临界电气元件上的流出。 在本发明的一个实施例中，表面可以包括由阻焊剂覆盖的第一部分，其具有由接合焊盘填充的区域和被封装的第二部分。 通过在接近第二部分的阻焊剂中形成开口以在其到达接合焊盘之前收集密封剂来防止接合焊盘上的封装流动。
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公开(公告)号：US06521980B1
公开(公告)日：2003-02-18
申请号：US09679095
申请日：2000-10-04
申请人： Patrick W. Tandy , Joseph M. Brand , Brad D. Rumsey , Steven R. Stephenson , David J. Corisis , Todd O. Bolken , Edward A. Schrock , Brenton L. Dickey
发明人： Patrick W. Tandy , Joseph M. Brand , Brad D. Rumsey , Steven R. Stephenson , David J. Corisis , Todd O. Bolken , Edward A. Schrock , Brenton L. Dickey
IPC分类号： H01L2348
CPC分类号： H01L23/3107 , H01L21/565 , H01L23/3157 , H01L23/4985 , H01L24/48 , H01L2224/05599 , H01L2224/4824 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.
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公开(公告)号：US06210992B1
公开(公告)日：2001-04-03
申请号：US09386971
申请日：1999-08-31
申请人： Patrick W. Tandy , Joseph M. Brand , Brad D. Rumsey , Steven R. Stephenson , David J. Corisis , Todd O. Bolken , Edward A. Schrock , Brenton L. Dickey
发明人： Patrick W. Tandy , Joseph M. Brand , Brad D. Rumsey , Steven R. Stephenson , David J. Corisis , Todd O. Bolken , Edward A. Schrock , Brenton L. Dickey
IPC分类号： H01L2144
CPC分类号： H01L23/3107 , H01L21/565 , H01L23/3157 , H01L23/4985 , H01L24/48 , H01L2224/05599 , H01L2224/4824 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.
摘要翻译： 集成电路封装可以部分地形成有封装区域。 可以通过提供在封装区域和关键部件所在的区域之间收集密封剂流出物的空腔来防止密封剂在临界电气元件上的流出。 在本发明的一个实施例中，表面可以包括由阻焊剂覆盖的第一部分，其具有由接合焊盘填充的区域和被封装的第二部分。 通过在接近第二部分的阻焊剂中形成开口以在其到达接合焊盘之前收集密封剂来防止接合焊盘上的封装流动。
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公开(公告)号：US06365434B1
公开(公告)日：2002-04-02
申请号：US09605582
申请日：2000-06-28
IPC分类号： H01L2144
CPC分类号： H01L21/565 , H01L2924/0002 , Y10T428/24273 , Y10T428/24777 , H01L2924/00
摘要： A method and apparatus for encapsulating microelectronic devices. In one embodiment, a microelectronic device is engaged with a support member having a first edge, a second edge opposite the first edge, and an engaging surface with at least a portion of the engaging surface spaced apart from the first and second edges. The first edge of the support member is positioned proximate to a wall of a mold and an aligning member is moved relative to the wall of the mold to contact the engaging surface of the support member and bias the first edge of the support member against the wall of the mold. The microelectronic device is then encapsulated by disposing an encapsulating material in the mold adjacent to the microelectronic device. By biasing the first edge of the support member against the wall of the mold, the method can prevent encapsulating material from passing between the first edge of the support member and the wall of the mold, where the encapsulating material would otherwise form flash. Accordingly, a method and apparatus in accordance with an embodiment of the invention can reduce or eliminate flash adjacent to the first edge of the support member.
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公开(公告)号：US06644949B2
公开(公告)日：2003-11-11
申请号：US09904240
申请日：2001-07-11
IPC分类号： B29C4514
CPC分类号： H01L21/565 , H01L2924/0002 , Y10T428/24273 , Y10T428/24777 , H01L2924/00
摘要： A method and apparatus for encapsulating microelectronic devices. In one embodiment, a microelectronic device is engaged with a support member having a first edge, a second edge opposite the first edge, and an engaging surface with at least a portion of the engaging surface spaced apart from the first and second edges. The first edge of the support member is positioned proximate to a wall of a mold and an aligning member is moved relative to the wall of the mold to contact the engaging surface of the support member and bias the first edge of the support member against the wall of the mold. The microelectronic device is then encapsulated by disposing an encapsulating material in the mold adjacent to the microelectronic device. By biasing the first edge of the support member against the wall of the mold, the method can prevent encapsulating material from passing between the first edge of the support member and the wall of the mold, where the encapsulating material would otherwise form flash. Accordingly, a method and apparatus in accordance with an embodiment of the invention can reduce or eliminate flash adjacent to the first edge of the support member.
摘要翻译： 一种用于封装微电子器件的方法和装置。 在一个实施例中，微电子器件与具有第一边缘，与第一边缘相对的第二边缘的支撑构件以及与第一和第二边缘间隔开的接合表面的至少一部分的接合表面接合。 支撑构件的第一边缘定位成靠近模具的壁并且对准构件相对于模具的壁移动以接触支撑构件的接合表面并将支撑构件的第一边缘抵靠壁 的模具。 然后通过将密封材料设置在与微电子器件相邻的模具中来封装微电子器件。 通过将支撑构件的第一边缘偏置在模具的壁上，该方法可以防止包封材料通过支撑构件的第一边缘和模具的壁之间，其中封装材料将形成闪光。 因此，根据本发明的实施例的方法和装置可以减少或消除与支撑构件的第一边缘相邻的闪光。
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公开(公告)号：US06638595B2
公开(公告)日：2003-10-28
申请号：US09903994
申请日：2001-07-11
IPC分类号： H01L2144
CPC分类号： H01L21/565 , H01L2924/0002 , Y10T428/24273 , Y10T428/24777 , H01L2924/00
摘要： A method and apparatus for encapsulating microelectronic devices. In one embodiment, a microelectronic device is engaged with a support member having a first edge, a second edge opposite the first edge, and an engaging surface with at least a portion of the engaging surface spaced apart from the first and second edges. The first edge of the support member is positioned proximate to a wall of a mold and an aligning member is moved relative to the wall of the mold to contact the engaging surface of the support member and bias the first edge of the support member against the wall of the mold. The microelectronic device is then encapsulated by disposing an encapsulating material in the mold adjacent to the microelectronic device. By biasing the first edge of the support member against the wall of the mold, the method can prevent encapsulating material from passing between the first edge of the support member and the wall of the mold, where the encapsulating material would otherwise form flash. Accordingly, a method and apparatus in accordance with an embodiment of the invention can reduce or eliminate flash adjacent to the first edge of the support member.
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公开(公告)号：US06660558B1
公开(公告)日：2003-12-09
申请号：US09847470
申请日：2001-05-02
IPC分类号： H01L2144
CPC分类号： H01L21/565 , H01L23/3107 , H01L24/48 , H01L2224/05599 , H01L2224/48091 , H01L2224/4824 , H01L2224/85444 , H01L2224/85455 , H01L2924/00014 , H01L2924/01039 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A method for fabricating a semiconductor package is performed using a mold tooling fixture having a mold cavity and a pair of flash control cavities on either side of the mold cavity. The semiconductor package includes a substrate and a semiconductor die attached to the substrate. The substrate includes a pattern of conductors wire bonded to the die, and an array of solder balls bonded to ball bonding pads on the conductors. In addition, the substrate includes a die encapsulant encapsulating the die, and a wire bond encapsulant encapsulating the wire bonds. During molding of the wire bond encapsulant, the flash control cavities collect flash, and provide pressure relief for venting the mold cavity. In addition, the flash control cavities restrict the flash to a selected area of the package substrate, such that the ball bonding pads and solder balls are not contaminated.
摘要翻译： 使用具有模腔和在模腔两侧的一对闪光控制腔的模具工具来进行制造半导体封装的方法。 半导体封装包括衬底和附着于衬底的半导体管芯。 衬底包括导线接合到管芯的导体图案，以及焊接在导体上的焊球的焊球阵列。 此外，衬底包括封装管芯的管芯密封剂和封装引线接合的引线键合密封剂。 在线焊密封剂的模制期间，闪光控制腔收集闪光，并为排气模腔提供压力释放。 此外，闪光控制腔将闪光灯限制到封装衬底的选定区域，使得球焊垫和焊球不被污染。
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8.发明授权Method for fabricating semiconductor packages using mold tooling fixture with flash control cavities 有权使用具有闪光控制腔的模具夹具制造半导体封装的方法公开(公告)号：US06331453B1
公开(公告)日：2001-12-18
申请号：US09465350
申请日：1999-12-16
IPC分类号： H01L2144
CPC分类号： H01L21/565 , H01L23/3107 , H01L24/48 , H01L2224/05599 , H01L2224/48091 , H01L2224/4824 , H01L2224/85444 , H01L2224/85455 , H01L2924/00014 , H01L2924/01039 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A method for fabricating a semiconductor package is performed using a mold tooling fixture having a mold cavity and a pair of flash control cavities on either side of the mold cavity. The semiconductor package includes a substrate and a semiconductor die attached to the substrate. The substrate includes a pattern of conductors wire bonded to the die, and an array of solder balls bonded to ball bonding pads on the conductors. In addition, the substrate includes a die encapsulant encapsulating the die, and a wire bond encapsulant encapsulating the wire bonds. During molding of the wire bond encapsulant, the flash control cavities collect flash, and provide pressure relief for venting the mold cavity. In addition, the flash control cavities restrict the flash to a selected area of the package substrate, such that the ball bonding pads and solder balls are not contaminated.
摘要翻译： 使用具有模腔和在模腔两侧的一对闪光控制腔的模具工具来进行制造半导体封装的方法。 半导体封装包括衬底和附着于衬底的半导体管芯。 衬底包括导线接合到管芯的导体图案，以及焊接在导体上的焊球的焊球阵列。 此外，衬底包括封装管芯的管芯密封剂和封装引线接合的引线键合密封剂。 在线焊密封剂的模制期间，闪光控制腔收集闪光，并为排气模腔提供压力释放。 此外，闪光控制腔将闪光灯限制到封装衬底的选定区域，使得焊球焊盘和焊球不被污染。
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公开(公告)号：US06518654B1
公开(公告)日：2003-02-11
申请号：US09834415
申请日：2001-04-13
IPC分类号： H01L2302
CPC分类号： H01L21/561 , H01L21/565 , H01L23/3107 , H01L24/32 , H01L24/48 , H01L24/97 , H01L2224/05599 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/30107 , H05K3/303 , H05K3/305 , H05K3/3436 , H05K2201/10568 , H05K2201/10734 , H05K2201/10977 , H05K2201/2036 , Y02P70/613 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the substrate. Encapsulation of the substrate edge by the cover reduces penetration of moisture or other contaminants into the substrate. The cover includes a rib that extends to contact a circuit board to which the ball grid array assembly is connected. With such a rib, planarity between the circuit board and the substrate is maintained during soldering.
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公开(公告)号：US07459773B2
公开(公告)日：2008-12-02
申请号：US11268095
申请日：2005-11-07
IPC分类号： H01L23/02
CPC分类号： H05K3/303 , H01L25/105 , H01L25/18 , H01L2225/1023 , H01L2225/1058 , H01L2225/1082 , H01L2924/0002 , H01L2924/15311 , H01L2924/3011 , H05K2201/10515 , H05K2201/10734 , H05K2203/167 , Y02P70/613 , H01L2924/00
摘要： A memory package having a plurality of vertically stacked ball grid arrays. Each of the vertically stacked ball grid arrays has a memory chip coupled thereto. Further, each of the plurality of ball grid arrays includes non-metal mateable alignment features. Each of the plurality of ball grid arrays is coupled to another of the plurality of ball grid arrays to from the vertically stacked memory package.
摘要翻译： 一种具有多个垂直堆叠的球栅阵列的存储器封装。 每个垂直堆叠的球栅阵列具有与其耦合的存储芯片。 此外，多个球栅阵列中的每一个包括非金属可对准的对准特征。 多个球栅阵列中的每一个耦合到多个球栅阵列中的另一个，以从垂直堆叠的存储器封装。
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