公开(公告)号：US06638595B2

公开(公告)日：2003-10-28

申请号：US09903994

申请日：2001-07-11

申请人： Brad D. Rumsey ,  Todd O. Bolken ,  Cary J. Baerlocher

发明人： Brad D. Rumsey ,  Todd O. Bolken ,  Cary J. Baerlocher

IPC分类号： H01L2144

CPC分类号： H01L21/565 ,  H01L2924/0002 ,  Y10T428/24273 ,  Y10T428/24777 ,  H01L2924/00

摘要： A method and apparatus for encapsulating microelectronic devices. In one embodiment, a microelectronic device is engaged with a support member having a first edge, a second edge opposite the first edge, and an engaging surface with at least a portion of the engaging surface spaced apart from the first and second edges. The first edge of the support member is positioned proximate to a wall of a mold and an aligning member is moved relative to the wall of the mold to contact the engaging surface of the support member and bias the first edge of the support member against the wall of the mold. The microelectronic device is then encapsulated by disposing an encapsulating material in the mold adjacent to the microelectronic device. By biasing the first edge of the support member against the wall of the mold, the method can prevent encapsulating material from passing between the first edge of the support member and the wall of the mold, where the encapsulating material would otherwise form flash. Accordingly, a method and apparatus in accordance with an embodiment of the invention can reduce or eliminate flash adjacent to the first edge of the support member.

公开(公告)号：US06365434B1

公开(公告)日：2002-04-02

申请号：US09605582

申请日：2000-06-28

申请人： Brad D. Rumsey ,  Todd O. Bolken ,  Cary J. Baerlocher

发明人： Brad D. Rumsey ,  Todd O. Bolken ,  Cary J. Baerlocher

IPC分类号： H01L2144

CPC分类号： H01L21/565 ,  H01L2924/0002 ,  Y10T428/24273 ,  Y10T428/24777 ,  H01L2924/00

摘要： A method and apparatus for encapsulating microelectronic devices. In one embodiment, a microelectronic device is engaged with a support member having a first edge, a second edge opposite the first edge, and an engaging surface with at least a portion of the engaging surface spaced apart from the first and second edges. The first edge of the support member is positioned proximate to a wall of a mold and an aligning member is moved relative to the wall of the mold to contact the engaging surface of the support member and bias the first edge of the support member against the wall of the mold. The microelectronic device is then encapsulated by disposing an encapsulating material in the mold adjacent to the microelectronic device. By biasing the first edge of the support member against the wall of the mold, the method can prevent encapsulating material from passing between the first edge of the support member and the wall of the mold, where the encapsulating material would otherwise form flash. Accordingly, a method and apparatus in accordance with an embodiment of the invention can reduce or eliminate flash adjacent to the first edge of the support member.

公开(公告)号：US06644949B2

公开(公告)日：2003-11-11

申请号：US09904240

申请日：2001-07-11

申请人： Brad D. Rumsey ,  Todd O. Bolken ,  Cary J. Baerlocher

发明人： Brad D. Rumsey ,  Todd O. Bolken ,  Cary J. Baerlocher

IPC分类号： B29C4514

CPC分类号： H01L21/565 ,  H01L2924/0002 ,  Y10T428/24273 ,  Y10T428/24777 ,  H01L2924/00

摘要： A method and apparatus for encapsulating microelectronic devices. In one embodiment, a microelectronic device is engaged with a support member having a first edge, a second edge opposite the first edge, and an engaging surface with at least a portion of the engaging surface spaced apart from the first and second edges. The first edge of the support member is positioned proximate to a wall of a mold and an aligning member is moved relative to the wall of the mold to contact the engaging surface of the support member and bias the first edge of the support member against the wall of the mold. The microelectronic device is then encapsulated by disposing an encapsulating material in the mold adjacent to the microelectronic device. By biasing the first edge of the support member against the wall of the mold, the method can prevent encapsulating material from passing between the first edge of the support member and the wall of the mold, where the encapsulating material would otherwise form flash. Accordingly, a method and apparatus in accordance with an embodiment of the invention can reduce or eliminate flash adjacent to the first edge of the support member.

摘要翻译： 一种用于封装微电子器件的方法和装置。 在一个实施例中，微电子器件与具有第一边缘，与第一边缘相对的第二边缘的支撑构件以及与第一和第二边缘间隔开的接合表面的至少一部分的接合表面接合。 支撑构件的第一边缘定位成靠近模具的壁并且对准构件相对于模具的壁移动以接触支撑构件的接合表面并将支撑构件的第一边缘抵靠壁 的模具。 然后通过将密封材料设置在与微电子器件相邻的模具中来封装微电子器件。 通过将支撑构件的第一边缘偏置在模具的壁上，该方法可以防止包封材料通过支撑构件的第一边缘和模具的壁之间，其中封装材料将形成闪光。 因此，根据本发明的实施例的方法和装置可以减少或消除与支撑构件的第一边缘相邻的闪光。

公开(公告)号：US06395579B2

公开(公告)日：2002-05-28

申请号：US09789892

申请日：2001-02-21

申请人： Patrick W. Tandy ,  Joseph M. Brand ,  Brad D. Rumsey ,  Steven R. Stephenson ,  David J. Corisis ,  Todd O. Bolken ,  Edward A. Schrock ,  Brenton L. Dickey

发明人： Patrick W. Tandy ,  Joseph M. Brand ,  Brad D. Rumsey ,  Steven R. Stephenson ,  David J. Corisis ,  Todd O. Bolken ,  Edward A. Schrock ,  Brenton L. Dickey

IPC分类号： H01L2144

CPC分类号： H01L23/3107 ,  H01L21/565 ,  H01L23/3157 ,  H01L23/4985 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/4824 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

摘要翻译： 集成电路封装可以部分地形成有封装区域。 可以通过提供在封装区域和关键部件所在的区域之间收集密封剂流出物的空腔来防止密封剂在临界电气元件上的流出。 在本发明的一个实施例中，表面可以包括由阻焊剂覆盖的第一部分，其具有由接合焊盘填充的区域和被封装的第二部分。 通过在接近第二部分的阻焊剂中形成开口以在其到达接合焊盘之前收集密封剂来防止接合焊盘上的封装流动。

公开(公告)号：US06521980B1

公开(公告)日：2003-02-18

申请号：US09679095

申请日：2000-10-04

申请人： Patrick W. Tandy ,  Joseph M. Brand ,  Brad D. Rumsey ,  Steven R. Stephenson ,  David J. Corisis ,  Todd O. Bolken ,  Edward A. Schrock ,  Brenton L. Dickey

发明人： Patrick W. Tandy ,  Joseph M. Brand ,  Brad D. Rumsey ,  Steven R. Stephenson ,  David J. Corisis ,  Todd O. Bolken ,  Edward A. Schrock ,  Brenton L. Dickey

IPC分类号： H01L2348

CPC分类号： H01L23/3107 ,  H01L21/565 ,  H01L23/3157 ,  H01L23/4985 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/4824 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

公开(公告)号：US06210992B1

公开(公告)日：2001-04-03

申请号：US09386971

申请日：1999-08-31

申请人： Patrick W. Tandy ,  Joseph M. Brand ,  Brad D. Rumsey ,  Steven R. Stephenson ,  David J. Corisis ,  Todd O. Bolken ,  Edward A. Schrock ,  Brenton L. Dickey

发明人： Patrick W. Tandy ,  Joseph M. Brand ,  Brad D. Rumsey ,  Steven R. Stephenson ,  David J. Corisis ,  Todd O. Bolken ,  Edward A. Schrock ,  Brenton L. Dickey

IPC分类号： H01L2144

CPC分类号： H01L23/3107 ,  H01L21/565 ,  H01L23/3157 ,  H01L23/4985 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/4824 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

摘要翻译： 集成电路封装可以部分地形成有封装区域。 可以通过提供在封装区域和关键部件所在的区域之间收集密封剂流出物的空腔来防止密封剂在临界电气元件上的流出。 在本发明的一个实施例中，表面可以包括由阻焊剂覆盖的第一部分，其具有由接合焊盘填充的区域和被封装的第二部分。 通过在接近第二部分的阻焊剂中形成开口以在其到达接合焊盘之前收集密封剂来防止接合焊盘上的封装流动。

公开(公告)号：US06690086B2

公开(公告)日：2004-02-10

申请号：US10318172

申请日：2002-12-13

申请人： Stephen L. James ,  Brad D. Rumsey

发明人： Stephen L. James ,  Brad D. Rumsey

IPC分类号： H01L2302

CPC分类号： H01L23/562 ,  H01L21/565 ,  H01L23/13 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for inhibiting damage caused to semiconductor die packages during a molding process, and the semiconductor die packages formed therefrom, is described. One or more openings are provided in a die carrier which are filled with a material which is more resistant to compressive forces than the carrier.

摘要翻译： 描述了一种用于抑制在模制过程中对半导体模具封装造成的损坏的方法以及由其形成的半导体管芯封装。 一个或多个开口设置在模具载体中，其中填充有比载体更耐压缩力的材料。

公开(公告)号：US06668449B2

公开(公告)日：2003-12-30

申请号：US09888674

申请日：2001-06-25

申请人： Brad D. Rumsey ,  Matt E. Schwab

发明人： Brad D. Rumsey ,  Matt E. Schwab

IPC分类号： H05K334

CPC分类号： H01L24/49 ,  B33Y10/00 ,  B33Y80/00 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/05553 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73215 ,  H01L2224/85207 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/0266 ,  H05K3/0008 ,  H05K3/0052 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/09918 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49222 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention features a novel design for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided. Preferably, the pin one indicator/alignment fiducial is placed adjacent a comer area of a ball grid array, and comprises an “L”-shaped narrow opening in a solder mask layer in which two lines, mutually perpendicular to one another, form components of an X-Y axis. The pin one indicator/alignment fiducial of the present invention is configured to provide only a minimal opening in the solder resist, making smaller pitches between solder balls and tighter dimensional controls possible. Therefore, the present invention is particularly useful for packages in which the solder resist surface of the mounting substrate is heavily populated with solder ball contact pads and/or and solder balls, and/or in applications where the chip outline is nearly the same size as the package (e.g., Chip Scale Packages (CSP), Near Chip Size (NCS), etc.).

摘要翻译： 本发明的特征在于用于基准和引脚一指示器的新颖设计，其利用管芯安装衬底中的单个阻焊剂开口来执行现有技术基准和引脚一指示器的组合功能。 还提供了使用组合销一个指示器和本发明的对准基准来制造载体基板并制造半导体器件封装的方法。 优选地，销一个指示器/对准基准邻近球栅阵列的拐角区域放置，并且在焊接掩模层中包括“L”形窄的开口，其中彼此相互垂直的两条线形成 XY轴。 本发明的针脚指示器/对准基准被配置为仅在阻焊剂中提供最小的开口，从而使焊球之间的较小的间距和更紧密的尺寸控制成为可能。 因此，本发明特别适用于其中安装基板的阻焊剂表面大量地填充有焊球接触焊盘和/或焊球的封装，和/或在芯片轮廓尺寸与 封装（例如，芯片尺寸封装（CSP），近芯片尺寸（NCS）等）。

公开(公告)号：US06634099B2

公开(公告)日：2003-10-21

申请号：US09854073

申请日：2001-05-11

申请人： Brad D. Rumsey

发明人： Brad D. Rumsey

IPC分类号： H05K334

CPC分类号： H05K3/3452 ,  H05K2201/0989 ,  H05K2203/1178 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49165

摘要： A multilayer circuit board includes a base layer, a conductive layer and a soldermask. The soldermask layer has two sets of openings. One of the openings are vent openings, that expose the base layer to provide ventilation so that gases may escape during processing. The second openings expose selective regions of a conductor layer. The multi-layer circuit board provides for less occurrences of delamination.

公开(公告)号：US07263768B2

公开(公告)日：2007-09-04

申请号：US10927253

申请日：2004-08-25

申请人： Brad D. Rumsey ,  Matt E. Schwab

发明人： Brad D. Rumsey ,  Matt E. Schwab

IPC分类号： H05K3/34 ,  H05K1/03

CPC分类号： H01L24/49 ,  B33Y10/00 ,  B33Y80/00 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2224/05553 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/4911 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73215 ,  H01L2224/85207 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H05K1/0266 ,  H05K3/0008 ,  H05K3/0052 ,  H05K3/3452 ,  H05K2201/0989 ,  H05K2201/09918 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49169 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/49222 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： The present invention features a novel design for a fiducial and pin one indicator that utilizes a single solder resist opening in a die mounting substrate to perform the combined functions of prior art fiducials and pin one indicators. Methods of fabricating a carrier substrate and fabricating a semiconductor device package using the combination pin one indicator and alignment fiducial of the present invention are also provided.

摘要翻译： 本发明的特征在于用于基准和引脚一指示器的新颖设计，其利用管芯安装衬底中的单个阻焊剂开口来执行现有技术基准和引脚一指示器的组合功能。 还提供了使用组合销一个指示器和本发明的对准基准来制造载体基板并制造半导体器件封装的方法。