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公开(公告)号：US5990817A
公开(公告)日：1999-11-23
申请号：US956819
申请日：1997-10-23
申请人： Philippe Belin , Herve Marie
发明人： Philippe Belin , Herve Marie
CPC分类号： H03M1/1028 , H03M1/183
摘要： The invention relates to an A/D conversion device intended to supply at the output a digital signal Vout[0:7] resulting from the conversion of an analog input voltage Vin and receiving a control signal CRS used for defining the transfer characteristic of the device by way of comparison with the output signal Vout[0:7]. According to the invention, such a device comprises a reference module (AO, CMP2) which allows adjustment of the digital value of the output signal Vout[0:7] at a predetermined value when the analog input voltage Vin is zero, and means (Mx, Vact) for substituting for said voltage Vin a reference voltage Vref having a predetermined value when the device is in its control mode.
摘要翻译： 本发明涉及一种A / D转换装置，其旨在在输出端提供由模拟输入电压Vin的转换产生的数字信号Vout [0：7]，并接收用于定义装置的传送特性的控制信号CRS 通过与输出信号Vout [0:7]进行比较。 根据本发明，这种装置包括参考模块（AO，CMP2），当模拟输入电压Vin为零时，可以将输出信号Vout [0:7]的数字值调节到预定值， Mx，Vact），用于在设备处于其控制模式时，将具有预定值的参考电压Vref替换为所述电压Vin。
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公开(公告)号：US08804289B2
公开(公告)日：2014-08-12
申请号：US12682746
申请日：2008-10-13
申请人： Denis Crespo , Herve Marie , Nguyen Trieu Luan Le , Mickael Lucas
发明人： Denis Crespo , Herve Marie , Nguyen Trieu Luan Le , Mickael Lucas
IPC分类号： H02H9/04
CPC分类号： H01L27/0266 , H01L27/0259 , H02H9/046
摘要： A protection circuit (100, 700) is disclosed for protecting an integrated circuit having a first supply rail (Vcc) and a second supply rail (Vss) from exposure to an excessive voltage. The protection circuit (100, 700) comprises a sensor (120) for sensing a voltage increase on the first supply rail (Vcc). Such a sensor may be implemented as an RC element. The sensor (120) has an output coupled to a signal path for providing a detection signal on said path. The sensor (120) triggers a clamping circuit (180) to clamp the first supply rail (Vcc) to the second supply rail (Vss) in response to the detection signal, which typically signals an ESD event on the supply rails. A pre-amplifying stage (160) is coupled between the sensor (120) and the clamping circuit (180) to amplify the detection signal for the clamping circuit (180). The protection circuit further comprises a hold circuit (140) for holding the control input of the pre-amplifying stage (160) in an enabled state upon termination of the detection signal. Such a hold circuit may comprise a further RC element for accelerating the activation of the clamping circuit (180) and extending the activation of the clamping circuit beyond the termination of the detection signal, thus yielding a more efficient protection circuit (100, 700).
摘要翻译： 公开了一种用于保护具有第一电源轨（Vcc）和第二电源轨（Vss）的集成电路不被暴露于过电压的保护电路（100,700）。 保护电路（100,700）包括用于感测第一电源轨（Vcc）上的电压增加的传感器（120）。 这样的传感器可以被实现为RC元件。 传感器（120）具有耦合到信号路径的输出，用于在所述路径上提供检测信号。 响应于检测信号，传感器（120）触发钳位电路（180）将第一电源轨（Vcc）钳位到第二电源轨（Vss），该检测信号通常表示电源轨上的ESD事件。 预放大级（160）耦合在传感器（120）和钳位电路（180）之间，以放大钳位电路（180）的检测信号。 保护电路还包括保持电路（140），用于在检测信号终止时将预放大级（160）的控制输入保持在使能状态。 这种保持电路可以包括用于加速钳位电路（180）的激活并且将钳位电路的激活延伸超过检测信号的终止的另外的RC元件，从而产生更有效的保护电路（100,700）。
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公开(公告)号：US08290108B2
公开(公告)日：2012-10-16
申请号：US12357918
申请日：2009-01-22
申请人： Herve Marie
发明人： Herve Marie
IPC分类号： H03D3/24
CPC分类号： H03C3/0925 , H03C3/0941 , H03C3/095
摘要： A method for controlling a modulation signal for modulating a phase locked loop. A scaling control signal for scaling the modulation signal is generated using the error signal of the phase locked loop. The scaling control signal is adjusted when the modulation signal and the phase of the modulation signal have the same sign.
摘要翻译： 一种用于控制用于调制锁相环的调制信号的方法。 使用锁相环的误差信号产生用于缩放调制信号的缩放控制信号。 当调制信号和调制信号的相位具有相同符号时，调节缩放控制信号。
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公开(公告)号：US07629912B2
公开(公告)日：2009-12-08
申请号：US12096218
申请日：2006-12-04
申请人： Yann Le Guillou , Herve Marie
发明人： Yann Le Guillou , Herve Marie
IPC分类号： H03M3/00
摘要： An analog-to-digital converter (ADC1) of the Sigma Delta type provides a stream of digital output samples (OUT) in response to an analog input signal (IN). The analog-to-digital converter (ADC1) comprises a quantizer (QNT) that has a dead zone. The quantizer (QNT) provides a digital output sample that has a neutral value when the quantizer (QNT) receives an input signal whose amplitude is within the dead zone. A feedback path (DAC) within the analog-to-digital converter (ADC1) provides a feedback action only in response to a digital output sample that has a value other than the neutral value.
摘要翻译： Sigma Delta型的模数转换器（ADC1）响应于模拟输入信号（IN）提供数字输出采样流（OUT）。 模数转换器（ADC1）包括具有死区的量化器（QNT）。 当量化器（QNT）接收幅度在死区内的输入信号时，量化器（QNT）提供具有中性值的数字输出采样。 模数转换器（ADC1）内的反馈路径（DAC）仅响应于具有除中性值之外的值的数字输出采样来提供反馈动作。
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5.发明授权Integrated circuit comprising a phase-control loop with programmable phase shift 失效集成电路包括具有可编程相移的相位控制回路
公开(公告)号：US5949263A
公开(公告)日：1999-09-07
申请号：US54112
申请日：1998-04-02
申请人： Herve Marie
发明人： Herve Marie
CPC分类号： H03L7/183 , H03L7/081 , Y10S331/02
摘要： A known phase-control loop comprises an oscillator having a controllable frequency, a frequency divider and a phase comparator which compares a reference signal (CKREF) with the signal at the output of the frequency divider and controls the frequency of the oscillator.The circuit also comprises, at the output of the oscillator, a phase shifter which supplies a signal (CKN0) at a multiple frequency of the input frequency and shifted in phase with respect to the signal of the oscillator, and a synchronizing module which may be simply constituted by a D flipflop with the input D connected to the output of the divider, and the input CLK connected to the output of the phase shifter, and which supplies a signal (CKREF0) at the frequency of the input signal (CKREF) but is locked at the output signal of the phase shifter.
摘要翻译： 已知的相位控制回路包括具有可控频率的振荡器，分频器和相位比较器，其将参考信号（CKREF）与分频器的输出端的信号进行比较并控制振荡器的频率。 该电路在振荡器的输出端还包括一个移相器，该移相器提供输入频率的多个频率并相对于振荡器的信号同相移位的信号（CKN0），同步模块可以是 简单地由D触发器构成，其输入D连接到分频器的输出端，输入CLK连接到移相器的输出，并且以输入信号（CKREF）的频率提供信号（CKREF0），但是 被锁定在移相器的输出信号上。
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公开(公告)号：US08736393B2
公开(公告)日：2014-05-27
申请号：US13318915
申请日：2010-05-03
申请人： Guillaume Herault , Herve Marie
发明人： Guillaume Herault , Herve Marie
CPC分类号： H01L27/0808 , H01L23/5223 , H01L27/0207 , H01L27/0811 , H01L2924/0002 , H01L2924/00
摘要： A digitally controlled variable capacitance integrated electronic circuit module (100) comprises a set of basic cells in a matrix arrangement. Each basic cell itself comprises a functional block (11) which can be switched between two individual capacitance values, a control block (12), and a control junction connecting the control block and the functional block of said basic cell. The functional blocks and the control blocks are grouped into separate regions (110, 120) of the matrix arrangement, to reduce capacitive interaction between output paths and power supply paths of the module. The functional blocks can still be switched in a winding path order within the matrix arrangement. A module of the invention can be used in an oscillator capable of producing a signal at 4 GHz.
摘要翻译： 数字控制可变电容集成电子电路模块（100）包括矩阵布置中的一组基本单元。 每个基本单元本身包括可以在两个单独电容值之间切换的功能块（11），控制块（12）以及连接所述控制块和所述基本单元的功能块的控制结。 功能块和控制块被分组成矩阵布置的分离区域（110,120），以减少输出路径和模块的电源路径之间的电容性相互作用。 功能块仍然可以在矩阵布置内以绕组路径顺序切换。 本发明的模块可用于能够产生4GHz信号的振荡器。
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公开(公告)号：US08330630B2
公开(公告)日：2012-12-11
申请号：US13122753
申请日：2009-09-25
申请人： Herve Marie
发明人： Herve Marie
IPC分类号： H03M1/48
CPC分类号： H03K5/159 , G04F10/00 , G04F10/005 , H03D13/004 , H03K5/06 , H03K5/133 , H03L7/085
摘要： A circuit arrangement is described comprising a first receiver configured to receive a first input signal, a second receiver configured to receive a second input signal, a first signal generator configured to generate a first pulse signal, a second signal generator configured to generate a second pulse signal, wherein a delay between a rising edge of the first pulse signal and a rising edge of the second pulse signal is proportional to a difference between the first input signal and the second input signal, a first converter configured to convert the first pulse signal to a first digital number proportional to a width of the first pulse signal, a second converter configured to convert the second pulse signal to a second digital number proportional to a width of the second pulse signal, wherein at least one of the first converter and the second converter comprises a cascade of at least two converter stages, wherein each converter stage of the at least two converter stages is configured to propagate and shrink the respective pulse signal. Also a corresponding method is described.
摘要翻译： 描述了一种电路装置，其包括被配置为接收第一输入信号的第一接收器，被配置为接收第二输入信号的第二接收器，被配置为产生第一脉冲信号的第一信号发生器，被配置为产生第二脉冲 信号，其中所述第一脉冲信号的上升沿和所述第二脉冲信号的上升沿之间的延迟与所述第一输入信号和所述第二输入信号之间的差成比例，第一转换器，被配置为将所述第一脉冲信号转换为 与第一脉冲信号的宽度成比例的第一数字数字，被配置为将第二脉冲信号转换成与第二脉冲信号的宽度成比例的第二数字数字的第二转换器，其中第一转换器和第二转换器中的至少一个 转换器包括至少两个转换器级的级联，其中配置所述至少两个转换器级的每个转换器级 以传播和收缩相应的脉冲信号。 还描述了相应的方法。
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公开(公告)号：US20080309536A1
公开(公告)日：2008-12-18
申请号：US12096218
申请日：2006-12-04
申请人： Yann Le Guillou , Herve Marie
发明人： Yann Le Guillou , Herve Marie
IPC分类号： H03M3/02
摘要： An analog-to-digital converter (ADC1) of the Sigma Delta type provides a stream of digital output samples (OUT) in response to an analog input signal (IN). The analog-to-digital converter (ADC1) comprises a quantizer (QNT) that has a dead zone. The quantizer (QNT) provides a digital output sample that has a neutral value when the quantizer (QNT) receives an input signal whose amplitude is within the dead zone. A feedback path (DAC) within the analog-to-digital converter (ADC1) provides a feedback action only in response to a digital output sample that has a value other than the neutral value.
摘要翻译： Sigma Delta型的模数转换器（ADC1）响应于模拟输入信号（IN）提供数字输出采样流（OUT）。 模数转换器（ADC1）包括具有死区的量化器（QNT）。 当量化器（QNT）接收幅度在死区内的输入信号时，量化器（QNT）提供具有中性值的数字输出采样。 模数转换器（ADC1）内的反馈路径（DAC）仅响应于具有除中性值之外的值的数字输出采样来提供反馈动作。
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公开(公告)号：US5999026A
公开(公告)日：1999-12-07
申请号：US54113
申请日：1998-04-02
申请人： Pieter Vorenkamp , Herve Marie
发明人： Pieter Vorenkamp , Herve Marie
CPC分类号： H03L7/00
摘要： Starting from an input signal (data) and a clock signal (clk), this device supplies an output signal (CKREF0) identical to the input signal but resynchronized with the clock signal. It comprises two cascaded D-type flip-flops (63, 65), the clock signal of the second flip-flop being inverted (62) with respect to that of the first flip-flop. The first flip-flop has its output coupled to the data input of the second flip-flop via a multiplexer (64), which is controlled by a signal (d-Ph) containing information about the phase relationship between the input signal and the clock signal, in such a manner that either input signal or the signal from the first flip-flop is applied to the input of the second flip-flop. This device can be used in a known phase control loop comprising an oscillator whose frequency is controllable, a frequency divider, and a phase comparator.
摘要翻译： 从输入信号（数据）和时钟信号（clk）开始，该器件提供与输入信号相同但与时钟信号重新同步的输出信号（CKREF0）。 它包括两个级联的D型触发器（63,65），第二触发器的时钟信号相对于第一触发器的时钟信号反相（62）。 第一触发器经由多路复用器（64）将其输出耦合到第二触发器的数据输入，多路复用器（64）由包含有关输入信号和时钟之间的相位关系的信息的信号（d-Ph）控制 信号，使得输入信号或来自第一触发器的信号被施加到第二触发器的输入。 该器件可用于已知的相位控制环路，其包括其频率可控的振荡器，分频器和相位比较器。
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公开(公告)号：US20120032703A1
公开(公告)日：2012-02-09
申请号：US13201848
申请日：2010-02-16
申请人： Denis Crespo , Yves Dufour , Herve Marie
发明人： Denis Crespo , Yves Dufour , Herve Marie
IPC分类号： H03K19/00
摘要： A shrinking-pulse digital delay line (400) has a cascade of a plurality of stages (102,104) for modifying a width of a pulse propagating down the cascade (106 to 118). Each specific one of the stages has an input (106,116), an output (108,118) and a main path (110,112,120,122) between the input and the output. The main path has a first inverter (110,120) and a second inverter (112,122) connected in series via an intermediate node (114,124). Each specific stage has a third inverter (128,140) connected between the input and the intermediate node of a downstream stage in the cascade (102,104); and also has a fourth inverter (132,144) connected between the intermediate node of the specific stage (mode 114, stage 102, mode 124, stage 104) and the output (118, stage 104) of the downstream stage (stage 104).
摘要翻译： 收缩脉冲数字延迟线（400）具有级联的多级（102,104），用于修改沿级联（106至118）传播的脉冲的宽度。 每个特定的一个级在输入和输出之间具有输入（106,116），输出（108,118）和主路径（110,112,120,122）。 主路径具有通过中间节点（114,124）串联连接的第一反相器（110,120）和第二反相器（112,122）。 每个特定级具有连接在级联（102,104）中的下游级的输入和中间节点之间的第三反相器（128,140）。 并且还具有连接在特定级（模式114，级102，模式124，级104）的中间节点与下游级（级104）的输出（118，级104）之间的第四反相器（132,144）。
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