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1.发明授权Underfilling process in a molded matrix array package using flow front modifying solder resist 失效使用流动前修饰阻焊剂的模压矩阵阵列封装中的底部填充工艺公开(公告)号：US07151014B2
公开(公告)日：2006-12-19
申请号：US10774155
申请日：2004-02-05
IPC分类号： H01L23/31
CPC分类号： H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H05K3/3452 , H01L2924/00 , H01L2224/0401
摘要： Placing a flow modifier on a package substrate to create two flow fronts on a molded matrix array package. A flow modifier may be laid on a package substrate to a height that blocks off the bottom of other substrates (e.g., dice) coupled to the package substrate. By separating the top flow front and the bottom flow front, this process prevents the top flow front from wrapping around the sides of the substrates and trapping air below each substrate and in front of the bottom flow front.
摘要翻译： 将流动调节器放置在封装衬底上，以在模制的矩阵阵列封装上创建两个流动前沿。 流动改性剂可以铺设在封装衬底上，以阻止耦合到封装衬底的其它衬底（例如，裸片）的底部的高度。 通过分离顶部流动前部和底部流动前部，该过程防止顶部流动前部围绕基底的侧面包裹并且在每个基底之下并在底部流动前部的前方捕获空气。
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2.发明授权Underfilling process in a molded matrix array package using flow front modifying solder resist 有权使用流动前修饰阻焊剂的模压矩阵阵列封装中的底部填充工艺公开(公告)号：US07339276B2
公开(公告)日：2008-03-04
申请号：US10287318
申请日：2002-11-04
CPC分类号： H01L21/563 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H05K3/3452 , H01L2924/00 , H01L2224/0401
摘要： Placing a flow modifier on a package substrate to create two flow fronts on a molded matrix array package. A flow modifier may be laid on a package substrate to a height that blocks off the bottom of other substrates (e.g., dice) coupled to the package substrate. By separating the top flow front and the bottom flow front, this process prevents the top flow front from wrapping around the sides of the substrates and trapping air below each substrate and in front of the bottom flow front.
摘要翻译： 将流动调节器放置在封装衬底上，以在模制的矩阵阵列封装上创建两个流动前沿。 流动改性剂可以铺设在封装衬底上，以阻止耦合到封装衬底的其它衬底（例如，裸片）的底部的高度。 通过分离顶部流动前部和底部流动前部，该过程防止顶部流动前部围绕基底的侧面包裹并且在每个基底之下并在底部流动前部的前方捕获空气。
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公开(公告)号：US10043740B2
公开(公告)日：2018-08-07
申请号：US15208313
申请日：2016-07-12
申请人： Sri Ranga Sai Boyapati , Rahul N. Manepalli , Dilan Seneviratne , Srinivas V. Pietambaram , Kristof Darmawikarta , Robert Alan May , Islam A. Salama
发明人： Sri Ranga Sai Boyapati , Rahul N. Manepalli , Dilan Seneviratne , Srinivas V. Pietambaram , Kristof Darmawikarta , Robert Alan May , Islam A. Salama
IPC分类号： H01L23/48 , H01L23/498 , H01L21/02 , H01L21/48 , H01L23/00 , H01L25/065
摘要： Semiconductor packages with interconnects having passivation thereon is disclosed. The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.
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公开(公告)号：US08466559B2
公开(公告)日：2013-06-18
申请号：US12972161
申请日：2010-12-17
IPC分类号： H01L23/48
CPC分类号： H01L25/50 , H01L23/49816 , H01L23/5389 , H01L24/24 , H01L25/0657 , H01L2225/06527 , H01L2924/10253 , H01L2924/10523 , H01L2924/12042 , H01L2924/14 , H01L2924/00
摘要： Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a patterned die backside film (DBF) on a backside of a die, wherein the patterned DBF comprises an opening surrounding at least one through silicon via (TSV) pad disposed on the backside of the die.
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公开(公告)号：US20210305108A1
公开(公告)日：2021-09-30
申请号：US16832851
申请日：2020-03-27
申请人： Robert L. Sankman , Rahul N. Manepalli , Robert Alan May , Srinivas Venkata Ramanuja Pietambaram , Bharat P. Penmecha
发明人： Robert L. Sankman , Rahul N. Manepalli , Robert Alan May , Srinivas Venkata Ramanuja Pietambaram , Bharat P. Penmecha
IPC分类号： H01L23/15 , H01L25/065 , H01L23/538 , H01L23/31 , H01L21/48
摘要： Various examples provide a semiconductor patch. The patch includes a glass core having first and second opposed major surfaces extending in an x-y direction. The patch further includes a conductive via extending from the first major surface to the second major surface substantially in a z-direction. The patch further includes a bridge die embedded in a dielectric material in communication with the conductive via. The patch further includes an overmold at least partially encasing the glass core.
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公开(公告)号：US08508040B2
公开(公告)日：2013-08-13
申请号：US12957738
申请日：2010-12-01
申请人： Paul R. Start , Rahul N. Manepalli
发明人： Paul R. Start , Rahul N. Manepalli
CPC分类号： H01L21/50 , H01L21/563 , H01L23/367 , H01L23/42 , H01L23/4275 , H01L2224/73204
摘要： An integrated heat spreader (IHS) lid over a semiconductor die connected to a substrate forms a cavity. A bead of foaming material may be placed within the IHS cavity. During an IHS cure and reflow process the foaming material will expand and fill the IHS cavity and the foam's shape conforms to the various surface features present, encapsulating a thermal interface material (TIM) material, and increasing contact area of the foam sealant.
摘要翻译： 与衬底连接的半导体管芯上的集成散热器（IHS）盖形成空腔。 发泡材料珠可以放置在IHS腔内。 在IHS固化和回流工艺期间，发泡材料将膨胀并填充IHS腔，并且泡沫的形状符合存在的各种表面特征，包封热界面材料（TIM）材料，并增加泡沫密封剂的接触面积。
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7.发明申请公开(公告)号：US20120139093A1
公开(公告)日：2012-06-07
申请号：US12957738
申请日：2010-12-01
申请人： Paul R. Start , Rahul N. Manepalli
发明人： Paul R. Start , Rahul N. Manepalli
IPC分类号： H01L23/427 , H01L21/50
CPC分类号： H01L21/50 , H01L21/563 , H01L23/367 , H01L23/42 , H01L23/4275 , H01L2224/73204
摘要： An integrated heat spreader (IHS) lid over a semiconductor die connected to a substrate forms a cavity. A bead of foaming material may be placed within the IHS cavity. During an IHS cure and reflow process the foaming material will expand and fill the IHS cavity and the foam's shape conforms to the various surface features present, encapsulating a thermal interface material (TIM) material, and increasing contact area of the foam sealant.
摘要翻译： 与衬底连接的半导体管芯上的集成散热器（IHS）盖形成空腔。 发泡材料珠可以放置在IHS腔内。 在IHS固化和回流工艺期间，发泡材料将膨胀并填充IHS腔，并且泡沫的形状符合存在的各种表面特征，包封热界面材料（TIM）材料，并增加泡沫密封剂的接触面积。
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公开(公告)号：US20090004317A1
公开(公告)日：2009-01-01
申请号：US11772200
申请日：2007-06-30
CPC分类号： C09K5/14
摘要： A molding compound for use in an integrated circuit package comprises an epoxy and a thermally conductive filler material. The thermally conductive filler material comprises between 70% and 95% of the molding compound and has a thermal conductivity between 10 W/m-K and 3000 W/m-K.
摘要翻译： 用于集成电路封装的模塑料包括环氧树脂和导热填料。 该导热填料包含70％至95％的模塑料，其导热率在10W / m-K至3000W / m-K之间。
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公开(公告)号：US20200105731A1
公开(公告)日：2020-04-02
申请号：US16145620
申请日：2018-09-28
申请人： Aleksandar Aleksov , Sri Ranga Sai Boyapati , Kristof Darmawikarta , Rahul N. Manepalli , Robert Alan May , Srinivas V. Pietambaram
发明人： Aleksandar Aleksov , Sri Ranga Sai Boyapati , Kristof Darmawikarta , Rahul N. Manepalli , Robert Alan May , Srinivas V. Pietambaram
IPC分类号： H01L25/18 , H01L23/00 , H01L23/538 , H01L23/373
摘要： The present description addresses example methods for forming multi-chip microelectronic devices and the resulting devices. The multiple semiconductor die of the multichip package will be attached to a solid plate with a bonding system selected to withstand stresses applied when a mold material is applied to encapsulate the die of the multichip device. The solid plate will remain as a portion of the finished multi-chip device. The solid plate can be a metal plate to function as a heat spreader for the completed multi-chip device.
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10.发明授权Microelectronic package and stacked microelectronic assembly and computing system containing same 有权微电子封装和堆叠微电子组装和计算系统包含相同公开(公告)号：US09159649B2
公开(公告)日：2015-10-13
申请号：US13976102
申请日：2011-12-20
IPC分类号： H01L23/48 , H01L23/498 , H01L25/10
CPC分类号： H01L23/48 , H01L23/49816 , H01L23/49822 , H01L23/49894 , H01L23/562 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/01327 , H01L2924/15311 , H01L2924/1815 , H01L2924/18162 , H01L2924/3511 , H01L2924/00
摘要： A microelectronic package comprises a die (110, 210) and a plurality of electrically conductive layers (120, 220) and electrically insulating layers (130, 230), including a first electrically insulating layer (131, 231) closer to the die than any other electrically insulating layer) and second (132, 232) and third electrically insulating layers (233). Each electrically insulating layer has a corresponding glass transition temperature, coefficient of thermal expansion, and modulus of elasticity. The modulus of elasticity of the second electrically insulating layer is greater than that for the first electrically insulating layer, while CTE1 for the second electrically insulating layer is greater than CTE1 for the first. CTE2 for the third electrically insulating layer is less than CTE2 for the first electrically insulating layer. In an embodiment an electrically insulating layer is a glass cloth layer (140) that is an outermost layer of the microelectronic package.
摘要翻译： 微电子封装包括管芯（110,210）和多个导电层（120,220）和电绝缘层（130,230），其包括比任一个更靠近管芯的第一电绝缘层（131,231） 其它电绝缘层）和第二（132,232）和第三电绝缘层（233）。 每个电绝缘层具有相应的玻璃化转变温度，热膨胀系数和弹性模量。 第二电绝缘层的弹性模量大于第一电绝缘层的弹性模量，第二电绝缘层的CTE1大于第一电绝缘层的CTE1。 用于第三电绝缘层的CTE2小于第一电绝缘层的CTE2。 在一个实施例中，电绝缘层是作为微电子封装的最外层的玻璃布层（140）。
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