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    Circuit configuration for generating even-numbered duty factors
    7.
    发明授权
    Circuit configuration for generating even-numbered duty factors 失效
    用于产生偶数占空比的电路配置

    公开(公告)号：US5524037A

    公开(公告)日：1996-06-04

    申请号：US347886

    申请日：1994-12-01

    申请人： Gunter Donig ,  Edmund Goetz ,  Helmut Herrmann

    发明人： Gunter Donig ,  Edmund Goetz ,  Helmut Herrmann

    IPC分类号： H03K5/156 ,  H03K21/08 ,  H03K23/50 ,  H03K23/66

    CPC分类号： H03K21/08 ,  H03K23/505 ,  H03K5/1565

    摘要： A circuit configuration generates an even-numbered duty factor with an odd-numbered division n of a symmetrical clock signal. A first device generates a first output signal from the symmetrical clock signal. The first output signal begins upon each n.sup.th edge of one type, of a symmetrical clock signal and remains active for a length of N-1/2 periods of the symmetrical clock signal. A second device generates a second output signal from the symmetrical clock signal. The second output signal begins upon each n.sup.th edge of another type, of the symmetrical clock signal and remains active for the length of N-1/2 periods of the symmetrical clock signal. A logic linkage is connected to the first and second devices for linking the two output signals to form one symmetrical output signal.

    摘要翻译： 电路配置产生具有对称时钟信号的奇数分频n的偶数占空因数。 第一装置从对称时钟信号产生第一输出信号。 第一个输出信号从对称时钟信号的一种类型的每个第n个边沿开始，并且对称时钟信号的N-1/2个周期的长度保持有效。 第二装置从对称时钟信号产生第二输出信号。 第二个输出信号从对称时钟信号的另一种类型的第n个边缘开始，并且对称时钟信号的N-1/2个周期的长度保持有效。 逻辑联动装置连接到第一和第二装置，用于链接两个输出信号以形成一个对称的输出信号。

    Interleaving for mobile communications
    8.
    发明授权
    Interleaving for mobile communications 有权
    交错移动通信

    公开(公告)号：US07269149B2

    公开(公告)日：2007-09-11

    申请号：US10528604

    申请日：2002-09-24

    申请人： Ralf Kukla ,  Gerd Morsberger ,  Georg Sporlein ,  Gerhard Goedert ,  Edmund Goetz

    发明人： Ralf Kukla ,  Gerd Morsberger ,  Georg Sporlein ,  Gerhard Goedert ,  Edmund Goetz

    IPC分类号： H04Q7/00

    CPC分类号： H03M13/27 ,  H04L1/0045 ,  H04L1/0071

    摘要： A method for processing a bit sequence in a digital communication system, includes the steps of (a) storing the bits of said bit sequence at locations of a memory means indicated by a first interleaving scheme, (b) converting output bit positions into input bit positions according to an inverse of a second interleaving scheme, (c) reading out bits stored at locations of said memory means corresponding to said input bit positions, thereby generating an interleaved sequence which is interleaved according to said first and said second interleaving schemes, and (d) processing said interleaved sequence according to further physical processing steps. Alternatively, step (a) may include storing the bits of said input bit sequence in a memory means and step (b) may include converting output bit positions into input bit positions according to the inverse of a sequential application of a first interleaving scheme and a second interleaving scheme.

    摘要翻译： 一种用于处理数字通信系统中的比特序列的方法，包括以下步骤：（a）将所述比特序列的比特存储在由第一交织方案指示的存储器装置的位置处，（b）将输出比特位置转换成输入比特 根据第二交织方案的倒数，（c）读出存储在与所述输入比特位置对应的所述存储装置的位置处的比特，从而产生根据所述第一和所述第二交织方案进行交织的交错序列，以及 （d）根据进一步的物理处理步骤处理所述交错序列。 或者，步骤（a）可以包括将所述输入比特序列的比特存储在存储装置中，并且步骤（b）可以包括根据第一交织方案的顺序应用的反向将输出比特位置转换成输入比特位置 第二交织方案。

    Interleaving for mobile communications
    9.
    发明申请
    Interleaving for mobile communications 有权
    交错移动通信

    公开(公告)号：US20060140142A1

    公开(公告)日：2006-06-29

    申请号：US10528604

    申请日：2002-09-24

    申请人： Ralf Kukla ,  Gerd Morsberger ,  Georg Sporlein ,  Gerhard Goedert ,  Edmund Goetz

    发明人： Ralf Kukla ,  Gerd Morsberger ,  Georg Sporlein ,  Gerhard Goedert ,  Edmund Goetz

    IPC分类号： H04Q7/00

    CPC分类号： H03M13/27 ,  H04L1/0045 ,  H04L1/0071

    摘要： A method for processing a bit sequence in a digital communication system, includes the steps of (a) storing the bits of said bit sequence at locations of a memory means indicated by a first interleaving scheme, (b) converting output bit positions into input bit positions according to an inverse of a second interleaving scheme, (c) reading out bits stored at locations of said memory means corresponding to said input bit positions, thereby generating an interleaved sequence which is interleaved according to said first and said second interleaving schemes, and (d) processing said interleaved sequence according to further physical processing steps. Alternatively, step (a) may include storing the bits of said input bit sequence in a memory means and step (b) may include converting output bit positions into input bit positions according to the inverse of a sequential application of a first interleaving scheme and a second interleaving scheme.

    摘要翻译： 一种用于处理数字通信系统中的比特序列的方法，包括以下步骤：（a）将所述比特序列的比特存储在由第一交织方案指示的存储器装置的位置处，（b）将输出比特位置转换成输入比特 根据第二交织方案的倒数，（c）读出存储在与所述输入比特位置对应的所述存储装置的位置处的比特，从而产生根据所述第一和所述第二交织方案进行交织的交错序列，以及 （d）根据进一步的物理处理步骤处理所述交错序列。 或者，步骤（a）可以包括将所述输入比特序列的比特存储在存储装置中，并且步骤（b）可以包括根据第一交织方案的顺序应用的反向将输出比特位置转换成输入比特位置 第二交织方案。

    Frequency synthesizer with a phase-locked loop for receiving and processing signals in different frequency bands
    10.
    发明授权
    Frequency synthesizer with a phase-locked loop for receiving and processing signals in different frequency bands 有权
    具有锁相环的频率合成器，用于接收和处理不同频带的信号

    公开(公告)号：US06405024B1

    公开(公告)日：2002-06-11

    申请号：US09182278

    申请日：1998-10-29

    申请人： Edmund Goetz ,  Shen Feng ,  Markus Scholz ,  Georg Lipperer ,  Stefan Beyer

    发明人： Edmund Goetz ,  Shen Feng ,  Markus Scholz ,  Georg Lipperer ,  Stefan Beyer

    IPC分类号： H04B106

    CPC分类号： H03L7/23 ,  H04B1/403

    摘要： A frequency synthesizer for a radio terminal with which a dual-band and/or dual-mode switchover is possible in a simple manner. The frequency synthesizer has a double phase-locked loop with a high-frequency portion and an intermediate-frequency portion, each with one divider and one counter in a feedback branch. There is at least one memory for holding a plurality of divider values for the counter in the intermediate-frequency portion. The counter in the high-frequency portion is coupled to the memory in such a way that when a new divider value is written into the counter of the high-frequency portion, an associated divider value from the memory is written into the counter of the intermediate-frequency portion. In this way, the frequency generated by the intermediate-frequency divider is adapted to the frequency generated in the high-frequency portion in such a way that the requisite operating frequencies of each active mobile radio system are set automatically. In the same way, the dual-mode switchover can be carried out by coupling a further memory with further divider values for the counter of the high-frequency portion.

    摘要翻译： 一种用于无线终端的频率合成器，可以以简单的方式进行双频和/或双模切换。 频率合成器具有双重锁相环，其具有高频部分和中频部分，每个在反馈分支中具有一个分频器和一个计数器。 存在至少一个存储器，用于在中频部分中保存用于计数器的多个除法器值。 高频部分中的计数器以这样的方式耦合到存储器，即当新的分频器值被写入高频部分的计数器时，来自存储器的相关联的分频值被写入中间级的计数器 频率部分。 以这种方式，中频分频器产生的频率适应于高频部分中产生的频率，使得每个有源移动无线电系统的必要操作频率被自动设置。 以同样的方式，可以通过将另外的存储器与用于高频部分的计数器的另外的分频器值进行耦合来执行双模切换。