公开(公告)号：US20210118781A1

公开(公告)日：2021-04-22

申请号：US17060545

申请日：2020-10-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazunori HASEGAWA ,  Yuichi YATO ,  Hiroyuki NAKAMURA ,  Yukihiro SATO ,  Hiroya SHIMOYAMA

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device includes: a semiconductor chip including a field effect transistor for switching; a die pad on which the semiconductor chip is mounted via a first bonding material; a lead electrically connected to a pad for source of the semiconductor chip through a metal plate; a lead coupling portion formed integrally with the lead; and a sealing portion for sealing them. A back surface electrode for drain of the semiconductor chip and the die pad are bonded via the first bonding material, the metal plate and the pad for source of the semiconductor chip are bonded via a second bonding material, and the metal plate and the lead coupling portion are bonded via a third bonding material. The first, second, and third bonding materials have conductivity, and an elastic modulus of each of the first and second bonding materials is lower than that of the third bonding material.

公开(公告)号：US20140004661A1

公开(公告)日：2014-01-02

申请号：US14013304

申请日：2013-08-29

Applicant: Renesas Electronics Corporation

Inventor： Jumpei KONNO ,  Takafumi NISHITA ,  Nobuhiro KINOSHITA ,  Kazunori HASEGAWA ,  Michiaki SUGIYAMA

IPC: H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/48

Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Abstract translation: 为了提高半导体器件的可靠性，在倒装芯片接合工序中，事先将预先安装在突起电极的前端面上的焊料材料和预先施加在端子（接合引线）上的焊料材料） 加热并因此彼此集成并电连接。 端子包括具有第一宽度W1的宽部分（第一部分）和具有第二宽度W2的窄部分（第二部分）。 当焊料材料被加热时，布置在窄部分上的焊料材料的厚度变得小于布置在宽部分中的焊料材料的厚度。 然后，在倒装芯片接合工序中，将突出电极配置在狭窄部分上并粘合到窄部上。 因此，可以减少焊料材料的突出量。

公开(公告)号：US20140203431A1

公开(公告)日：2014-07-24

申请号：US14222649

申请日：2014-03-23

Applicant: Renesas Electronics Corporation

Inventor： Jumpei KONNO ,  Takafumi NISHITA ,  Nobuhiro KINOSHITA ,  Kazunori HASEGAWA ,  Michiaki SUGIYAMA

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/48

Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Abstract translation: 为了提高半导体器件的可靠性，在倒装芯片接合工序中，事先将预先安装在突起电极的前端面上的焊料材料和预先施加在端子（接合引线）上的焊料材料） 加热并因此彼此集成并电连接。 端子包括具有第一宽度W1的宽部分（第一部分）和具有第二宽度W2的窄部分（第二部分）。 当焊料材料被加热时，布置在窄部分上的焊料材料的厚度变得小于布置在宽部分中的焊料材料的厚度。 然后，在倒装芯片接合工序中，将突出电极配置在狭窄部分上并粘合到窄部上。 因此，可以减少焊料材料的突出量。

公开(公告)号：US20180247884A1

公开(公告)日：2018-08-30

申请号：US15558977

申请日：2015-07-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazunori HASEGAWA ,  Hiroi OKA

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49513 ,  H01L21/4825 ,  H01L21/52 ,  H01L23/3114 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/0603 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/37147 ,  H01L2224/37599 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/40245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83002 ,  H01L2224/83192 ,  H01L2224/8384 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/14252 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Reliability of a semiconductor device is improved. For this, embodied is a basic idea that a semiconductor chip (CHP1) mounted on an Ag layer (AGL) is fixed by using a temporarily fixing material (TA) having tackiness without forming the temporarily fixing material (TA) on a surface of the Ag layer (AGL) having a porous structure as much as possible, is realized. More specifically, the temporarily fixing material (TA) is supplied so as to have a portion made in contact with a chip mounting part (TAB), and the semiconductor chip (CHP1) is also mounted on the Ag layer (AGL) so that one portion of a rear surface of the semiconductor chip (CHP1) is made in contact with the temporarily fixing material (TA).