公开(公告)号：US20220013508A1

公开(公告)日：2022-01-13

申请号：US17486301

申请日：2021-09-27

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko AKIBA ,  Kenji SAKATA ,  Nobuhiro KINOSHITA ,  Yosuke KATSURA

IPC: H01L25/16 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498

Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.

公开(公告)号：US20220406700A1

公开(公告)日：2022-12-22

申请号：US17722823

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuhiro KINOSHITA ,  Shuuichi KARIYAZAKI ,  Keita TSUCHIYA

IPC: H01L23/498 ,  H01L23/66

Abstract: A wiring substrate includes: a first insulating layer; a first metal pattern formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first metal pattern; a second metal pattern formed on the second insulating layer; and an organic insulating film contacted with a portion of the second metal pattern. Also, the first metal pattern has: a first lower surface contacted with the first insulating layer; and a first upper surface contacted with the second insulating layer. Also, the second metal pattern has: a second lower surface contacted with the second insulating layer; and a second upper surface contacted with the organic insulating film. Further, a surface roughness of the second upper surface is larger than a surface roughness of each of the second lower surface, the first upper surface and the first lower surface.

公开(公告)号：US20200006303A1

公开(公告)日：2020-01-02

申请号：US16444933

申请日：2019-06-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko AKIBA ,  Kenji SAKATA ,  Nobuhiro KINOSHITA ,  Yosuke KATSURA

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00

Abstract: Reliability of a semiconductor device is improved. The semiconductor device PKG1 includes a wiring substrate SUB1, a semiconductor chip CHP1 and a capacitor CDC mounted on the upper surface 2t of the wiring substrate SUB1, and a lid LD formed of a metallic plate covering the semiconductor chip CHP1 and the wiring substrate SUB1. The semiconductor chip CHP1 is bonded to the lid LD via a conductive adhesive layer, and the capacitor CDC, which is thicker than the thickness of the semiconductor chip CHP1, is disposed in the cut off portion 4d1 provided in the lid LD, and is exposed from the lid LD.

公开(公告)号：US20150380345A1

公开(公告)日：2015-12-31

申请号：US14750009

申请日：2015-06-25

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiro ONO ,  Nobuhiro KINOSHITA ,  Tsuyoshi KIDA ,  Jumpei KONNO ,  Kenji SAKATA ,  Kentaro MORI ,  Shinji BABA

IPC: H01L23/495 ,  H01L23/544

CPC classification number: H01L23/49568 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49558 ,  H01L23/49811 ,  H01L23/544 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/06153 ,  H01L2224/06155 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8113 ,  H01L2224/81191 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/00011 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/32245 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2224/45147

Abstract: The reliability of a semiconductor device is improved. A probe mark is formed on a probe region of a pad covered with a protective insulating film. And, a pillar-shaped electrode has a first portion formed on an opening region and a second portion that is extended over the probe region from the upper portion of the opening region. At this time, a center position of the opening region is shifted from a center position of the pillar-shaped electrode that is opposed to a bonding finger.

Abstract translation: 提高了半导体器件的可靠性。 在覆盖有保护绝缘膜的焊盘的探针区域上形成探针标记。 并且，柱状电极具有形成在开口区域上的第一部分和从开口区域的上部在探针区域上延伸的第二部分。 此时，开口区域的中心位置从与接合手指相对的柱状电极的中心位置偏移。

公开(公告)号：US20140203431A1

公开(公告)日：2014-07-24

申请号：US14222649

申请日：2014-03-23

Applicant: Renesas Electronics Corporation

Inventor： Jumpei KONNO ,  Takafumi NISHITA ,  Nobuhiro KINOSHITA ,  Kazunori HASEGAWA ,  Michiaki SUGIYAMA

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/48

Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Abstract translation: 为了提高半导体器件的可靠性，在倒装芯片接合工序中，事先将预先安装在突起电极的前端面上的焊料材料和预先施加在端子（接合引线）上的焊料材料） 加热并因此彼此集成并电连接。 端子包括具有第一宽度W1的宽部分（第一部分）和具有第二宽度W2的窄部分（第二部分）。 当焊料材料被加热时，布置在窄部分上的焊料材料的厚度变得小于布置在宽部分中的焊料材料的厚度。 然后，在倒装芯片接合工序中，将突出电极配置在狭窄部分上并粘合到窄部上。 因此，可以减少焊料材料的突出量。

公开(公告)号：US20240120252A1

公开(公告)日：2024-04-11

申请号：US18358411

申请日：2023-07-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuhiro KINOSHITA ,  Mitsunobu WANSAWA

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3675 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/2929 ,  H01L2224/29324 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1631 ,  H01L2924/16598 ,  H01L2924/3512

Abstract: A semiconductor device according to one embodiment, includes: a wiring substrate having a core insulating layer; a semiconductor chip mounted on an upper surface of the wiring substrate; a plurality of solder balls formed on a lower surface of the wiring substrate; and a heat sink having a first portion fixed to a back surface of the semiconductor chip via a first adhesive layer, and a second portion located around the first portion and fixed to the wiring substrate via a second adhesive layer. Here, a portion of the plurality of solder balls is arranged at a position overlapping with each of the second portion of the heat sink and the second adhesive layer. Also, a second thickness of the second adhesive layer is greater than two times a first thickness of the first adhesive layer.

公开(公告)号：US20230411368A1

公开(公告)日：2023-12-21

申请号：US18461884

申请日：2023-09-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshihiko AKIBA ,  Kenji SAKATA ,  Nobuhiro KINOSHITA ,  Yosuke KATSURA

IPC: H01L25/16 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/165 ,  H01L25/105 ,  H01L24/32 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/83 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2224/32225 ,  H01L23/3675

Abstract: Reliability of a semiconductor device is improved. The semiconductor device includes a wiring substrate, a semiconductor chip and a capacitor mounted on the upper surface of the wiring substrate, and a lid formed of a metallic plate covering the semiconductor chip and the wire in substrate. The semiconductor chip is bonded to the lid via a conductive adhesive layer, and the capacitor, which is thicker than the thickness of the semiconductor chip, is disposed in the cut off portion provided in the lid, and is exposed from the lid.

公开(公告)号：US20140004661A1

公开(公告)日：2014-01-02

申请号：US14013304

申请日：2013-08-29

Applicant: Renesas Electronics Corporation

Inventor： Jumpei KONNO ,  Takafumi NISHITA ,  Nobuhiro KINOSHITA ,  Kazunori HASEGAWA ,  Michiaki SUGIYAMA

IPC: H01L23/00

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/85 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05554 ,  H01L2224/10175 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2224/1601 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81444 ,  H01L2224/83102 ,  H01L2224/85 ,  H01L2224/85203 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/48

Abstract: To improve reliability of a semiconductor device, in a flip-chip bonding step, a solder material that is attached to a tip end surface of a projecting electrode in advance and a solder material that is applied in advance over a terminal (bonding lead) are heated and thereby integrated and electrically connected to each other. The terminal includes a wide part (a first portion) with a first width W1 and a narrow part (a second portion) with a second width W2. When the solder material is heated, the thickness of the solder material arranged over the narrow part becomes smaller than the thickness of the solder material arranged in the wide part. Then, in the flip-chip bonding step, a projecting electrode is arranged over the narrow part and bonded onto the narrow part. Thus, the amount of protrusion of the solder material can be reduced.

Abstract translation: 为了提高半导体器件的可靠性，在倒装芯片接合工序中，事先将预先安装在突起电极的前端面上的焊料材料和预先施加在端子（接合引线）上的焊料材料） 加热并因此彼此集成并电连接。 端子包括具有第一宽度W1的宽部分（第一部分）和具有第二宽度W2的窄部分（第二部分）。 当焊料材料被加热时，布置在窄部分上的焊料材料的厚度变得小于布置在宽部分中的焊料材料的厚度。 然后，在倒装芯片接合工序中，将突出电极配置在狭窄部分上并粘合到窄部上。 因此，可以减少焊料材料的突出量。