公开(公告)号：US20060077751A1

公开(公告)日：2006-04-13

申请号：US11202314

申请日：2005-08-12

申请人： Reum Oh ,  Sang-bo Lee ,  Moo-sung Chae ,  Ho-young Song

发明人： Reum Oh ,  Sang-bo Lee ,  Moo-sung Chae ,  Ho-young Song

IPC分类号： G11C8/02

CPC分类号： G11C29/023 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254

摘要： In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the plurality of transfer signals such that a timing relationship is created between the transfer signals and the sampling clock signals. The latency circuit may further include a latency signal generator selectively storing the read information based on the sampling clock signals, and selectively outputting the stored read information as the latency signal based on the transfer signals. The latency signal generator may also delay the read information such that the delayed, read information is stored based on the sampling clock signals.

摘要翻译： 在一个实施例中，延迟电路基于CAS等待时间信息和读取信息生成等待时间信号。 例如，等待时间电路可以包括产生多个传送信号的时钟信号发生电路，并且基于并对应于多个传送信号产生多个采样时钟信号，使得在传送信号和传输信号之间产生定时关系 采样时钟信号。 延迟电路还可以包括等待时间信号发生器，其基于采样时钟信号选择性地存储读取的信息，并且基于传送信号选择性地输出存储的读取信息作为等待时间信号。 等待时间信号发生器还可以延迟读取信息，使得基于采样时钟信号来存储延迟读取信息。

公开(公告)号：US07298667B2

公开(公告)日：2007-11-20

申请号：US11202314

申请日：2005-08-12

申请人： Reum Oh ,  Sang-bo Lee ,  Moo-sung Chae ,  Ho-young Song

发明人： Reum Oh ,  Sang-bo Lee ,  Moo-sung Chae ,  Ho-young Song

IPC分类号： G11C8/00

CPC分类号： G11C29/023 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254

摘要： In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plurality of sampling clock signals based on and corresponding to the plurality of transfer signals such that a timing relationship is created between the transfer signals and the sampling clock signals. The latency circuit may further include a latency signal generator selectively storing the read information based on the sampling clock signals, and selectively outputting the stored read information as the latency signal based on the transfer signals. The latency signal generator may also delay the read information such that the delayed, read information is stored based on the sampling clock signals.

摘要翻译： 在一个实施例中，延迟电路基于CAS等待时间信息和读取信息生成等待时间信号。 例如，等待时间电路可以包括产生多个传送信号的时钟信号发生电路，并且基于并对应于多个传送信号产生多个采样时钟信号，使得在传送信号和传输信号之间产生定时关系 采样时钟信号。 延迟电路还可以包括等待时间信号发生器，其基于采样时钟信号选择性地存储读取的信息，并且基于传送信号选择性地输出存储的读取信息作为等待时间信号。 等待时间信号发生器还可以延迟读取信息，使得基于采样时钟信号来存储延迟读取信息。

公开(公告)号：US20080100335A1

公开(公告)日：2008-05-01

申请号：US11890673

申请日：2007-08-07

申请人： Sung-Ho Choi ,  Reum Oh

发明人： Sung-Ho Choi ,  Reum Oh

IPC分类号： H03K17/16

CPC分类号： G11C29/02 ,  G11C7/1048 ,  G11C29/025 ,  G11C29/028 ,  H03K19/0005

摘要： For determining an on die termination (ODT) mode in a semiconductor memory device, a first mode determining unit determines whether or not a normal ODT mode is enabled from performing a logic operation on a first set of signals. A second mode determining unit determines whether or not a dynamic ODT mode test is enabled from performing a logic operation on a second set of signals. One of the normal and dynamic ODT modes is enabled with more flexibility.

公开(公告)号：US20100008169A1

公开(公告)日：2010-01-14

申请号：US12585428

申请日：2009-09-15

申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC分类号： G11C7/00 ,  G11C8/00 ,  G11C8/18

CPC分类号： G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

摘要： A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

摘要翻译： 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号之一输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US07911862B2

公开(公告)日：2011-03-22

申请号：US12585428

申请日：2009-09-15

申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC分类号： G11C7/00

CPC分类号： G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

摘要： A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

摘要翻译： 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号之一输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US20100177582A1

公开(公告)日：2010-07-15

申请号：US12686176

申请日：2010-01-12

申请人： Myeong-O Kim ,  Jae-Won Ko ,  Reum Oh

发明人： Myeong-O Kim ,  Jae-Won Ko ,  Reum Oh

IPC分类号： G11C7/06 ,  G11C8/10 ,  G11C8/08 ,  G11C5/14

CPC分类号： G11C11/4096 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4097 ,  G11C2207/002

摘要： A semiconductor memory device is provided. A memory cell array has a plurality of memory cells connected between a plurality of word lines and a plurality of bit-line pairs. A sense amplifier unit has a plurality of sense amplifiers connected with the bit-line pairs respectively and amplifies data of the bit-line pairs to a sensing voltage level. A command decoder decodes a command applied from the outside and outputs the decoded command. A plurality of input/output (I/O) gates electrically connects the bit-line pairs with corresponding I/O line pairs in response to a voltage level applied through a plurality of corresponding column selection lines. A column decoder decodes a column address and drives at least one of the column selection lines to a plurality of different voltages levels.

摘要翻译： 提供半导体存储器件。 存储单元阵列具有连接在多个字线和多个位线对之间的多个存储单元。 读出放大器单元具有分别与位线对连接的多个读出放大器，并将位线对的数据放大到感测电压电平。 命令解码器解码从外部施加的命令并输出解码的命令。 响应于通过多个相应的列选择线施加的电压电平，多个输入/输出（I / O）门将位线对与对应的I / O线对电连接。 列解码器解码列地址并将列选择线中的至少一个驱动到多个不同的电压电平。

公开(公告)号：US07609584B2

公开(公告)日：2009-10-27

申请号：US11594807

申请日：2006-11-09

申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

摘要： A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

摘要翻译： 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号之一输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US20070115751A1

公开(公告)日：2007-05-24

申请号：US11594807

申请日：2006-11-09

申请人： Joung-Yeol Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

发明人： Joung-Yeol Kim ,  Seong-Jin Jang ,  Kyoung-Ho Kim ,  Sam-Young Bang ,  Reum Oh

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C7/1027 ,  G11C7/1045 ,  G11C7/1066 ,  G11C7/12 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4094

摘要： A latency control circuit and method thereof and auto-precharge control circuit and method thereof are provided. The example latency control circuit may include a master unit activating at least one master signal based on a reference signal and an internal clock signal and a plurality of slave units receiving the at least one master signal, each of the plurality of slave units receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals. The example method of latency control may include receiving at least one master signal, the received at least one master signal activated based on a reference signal and an internal clock signal and receiving a plurality of signals and outputting an output signal based at least in part upon one of the received plurality of signals and latency information. The example auto-precharge control circuit may include a precharge command delay unit generating a plurality of first precharge command delay signals in response to an internal clock signal and a write auto-precharge command signal, at least one bank address delay unit outputting a delayed bank address signal and a precharge main signal generator outputting a precharge main signal to banks based on the delayed bank address signal. The method of performing a precharging operation with the auto-precharge control circuit may include delaying a bank address signal based on a minimum time interval between executed memory commands and outputting a precharge main signal to one or more memory banks based on the delayed bank address signal.

摘要翻译： 提供了一种延迟控制电路及其方法和自动预充电控制电路及其方法。 示例性延迟控制电路可以包括基于参考信号和内部时钟信号来激活至少一个主信号的主单元和接收至少一个主信号的多个从单元，多个从单元中的每一个接收多个 并且至少部分地基于所接收的多个信号中的一个来输出输出信号。 等待时间控制的示例性方法可以包括：接收至少一个主信号，基于参考信号激活的所接收的至少一个主信号和内部时钟信号，并且接收多个信号并且至少部分地基于 所接收的多个信号和延迟信息中的一个。 示例性自动预充电控制电路可以包括预充电命令延迟单元，其响应于内部时钟信号和写自动预充电命令信号产生多个第一预充电命令延迟信号，至少一个存储体地址延迟单元输出延迟存储体 地址信号和预充电主信号发生器基于延迟的存储体地址信号向存储体输出预充电主信号。 利用自动预充电控制电路执行预充电操作的方法可以包括基于执行的存储器命令之间的最小时间间隔来延迟存储体地址信号，并且基于延迟的存储体地址信号向一个或多个存储器组输出预充电主信号 。

公开(公告)号：US06847559B2

公开(公告)日：2005-01-25

申请号：US10611255

申请日：2003-07-01

申请人： Reum Oh ,  Woo-Seop Jeong ,  Kyu-Hyoun Kim

发明人： Reum Oh ,  Woo-Seop Jeong ,  Kyu-Hyoun Kim

IPC分类号： H03K19/0175 ,  G11C7/10 ,  G11C11/406 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4093 ,  G11C7/00

CPC分类号： G11C7/1084 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4093

摘要： The present invention discloses an input buffer circuit of a synchronous semiconductor memory device comprising a differential amplifier type input buffer and a low current type input buffer, wherein the differential amplifier type input buffer is operated in a normal mode, and the low current type input buffer is operated in a self-refresh mode, thereby decreasing the current flowing through the input buffer in the self-refresh mode. According to the input buffer of the synchronous semiconductor memory device, the current flowing through the input buffer in the self-refresh mode is very small, therefore the power consumption of the synchronous semiconductor memory device can be reduced.

摘要翻译： 本发明公开了一种包括差分放大器型输入缓冲器和低电流型输入缓冲器的同步半导体存储器件的输入缓冲电路，其中差分放大器型输入缓冲器以正常模式工作，低电流型输入缓冲器 在自刷新模式下操作，从而在自刷新模式下减少流过输入缓冲器的电流。 根据同步半导体存储器件的输入缓冲器，在自刷新模式中流过输入缓冲器的电流非常小，因此可以降低同步半导体存储器件的功耗。

公开(公告)号：US08228748B2

公开(公告)日：2012-07-24

申请号：US12762620

申请日：2010-04-19

申请人： Taek-Seon Park ,  Reum Oh

发明人： Taek-Seon Park ,  Reum Oh

IPC分类号： G11C8/00

CPC分类号： G11C11/4076 ,  G11C8/18 ,  G11C2207/2272

摘要： A semiconductor memory device comprises a latency delay unit that toggles a delay clock signal on during a first interval between a time point where read burst signal is activated and a time point where a latency signal is activated, and subsequently toggling the delay clock signal on during a second interval between a time point where the read burst signal is inactivated and a time point where the latency signal is inactivated.

摘要翻译： 一种半导体存储器件包括等待延迟单元，其在读取脉冲串信号被激活的时间点和等待时间信号被激活的时间点之间的第一间隔期间切换延迟时钟信号，随后在延迟时间信号期间触发延迟时钟信号 读取脉冲串信号被去激活的时间点与等待时间信号被去激活的时间点之间的第二间隔。