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公开(公告)号:US20090212435A1
公开(公告)日:2009-08-27
申请号:US12036718
申请日:2008-02-25
IPC分类号: H01L23/532 , H01L21/768
CPC分类号: H01L24/11 , H01L21/56 , H01L24/02 , H01L24/10 , H01L24/13 , H01L29/41775 , H01L29/66734 , H01L29/78 , H01L29/7811 , H01L29/7813 , H01L2224/0401 , H01L2224/11019 , H01L2224/11466 , H01L2224/11831 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/05494 , H01L2924/13091 , H01L2924/00
摘要: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.
摘要翻译: 一种功率半导体器件及其制造方法,其包括在其有源区上的薄金属层和厚金属层的堆叠。
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公开(公告)号:US08791525B2
公开(公告)日:2014-07-29
申请号:US12036718
申请日:2008-02-25
IPC分类号: H01L29/76
CPC分类号: H01L24/11 , H01L21/56 , H01L24/02 , H01L24/10 , H01L24/13 , H01L29/41775 , H01L29/66734 , H01L29/78 , H01L29/7811 , H01L29/7813 , H01L2224/0401 , H01L2224/11019 , H01L2224/11466 , H01L2224/11831 , H01L2224/13 , H01L2224/13099 , H01L2224/16 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/05494 , H01L2924/13091 , H01L2924/00
摘要: A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the fabrication thereof.
摘要翻译: 一种功率半导体器件及其制造方法,其包括在其有源区上的薄金属层和厚金属层的堆叠。
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公开(公告)号:US08143729B2
公开(公告)日:2012-03-27
申请号:US12359735
申请日:2009-01-26
申请人: Mark Pavier , Danish Khatri , Daniel Cutler , Andrew Neil Sawle , Susan Johns , Martin Carroll , David Paul Jones
发明人: Mark Pavier , Danish Khatri , Daniel Cutler , Andrew Neil Sawle , Susan Johns , Martin Carroll , David Paul Jones
CPC分类号: H01L23/492 , H01L23/3114 , H01L23/3171 , H01L23/3192 , H01L24/05 , H01L24/12 , H01L2224/0401 , H01L2224/05541 , H01L2224/05552 , H01L2224/05553 , H01L2224/05555 , H01L2224/05558 , H01L2224/05567 , H01L2224/05572 , H01L2224/0558 , H01L2224/05599 , H01L2224/05639 , H01L2224/13007 , H01L2224/13021 , H01L2224/13022 , H01L2224/131 , H01L2224/16 , H01L2224/32245 , H01L2224/73153 , H01L2224/73253 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要: A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.
摘要翻译: 一种功率半导体封装,其包括具有阈值电压的功率半导体器件,所述阈值电压在进行高压釜测试时不变化。
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公开(公告)号:US20090218684A1
公开(公告)日:2009-09-03
申请号:US12359735
申请日:2009-01-26
申请人: Mark Pavier , Danish Khatri , Daniel Cutler , Andrew Neil Sawle , Susan Johns , Martin Carroll , David Paul Jones
发明人: Mark Pavier , Danish Khatri , Daniel Cutler , Andrew Neil Sawle , Susan Johns , Martin Carroll , David Paul Jones
IPC分类号: H01L23/498
CPC分类号: H01L23/492 , H01L23/3114 , H01L23/3171 , H01L23/3192 , H01L24/05 , H01L24/12 , H01L2224/0401 , H01L2224/05541 , H01L2224/05552 , H01L2224/05553 , H01L2224/05555 , H01L2224/05558 , H01L2224/05567 , H01L2224/05572 , H01L2224/0558 , H01L2224/05599 , H01L2224/05639 , H01L2224/13007 , H01L2224/13021 , H01L2224/13022 , H01L2224/131 , H01L2224/16 , H01L2224/32245 , H01L2224/73153 , H01L2224/73253 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H01L2924/00
摘要: A power semiconductor package that includes a power semiconductor device having a threshold voltage that does not vary when subjected to an autoclave test.
摘要翻译: 一种功率半导体封装,其包括具有阈值电压的功率半导体器件,所述阈值电压在进行高压釜测试时不变化。
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公开(公告)号:US06593172B2
公开(公告)日:2003-07-15
申请号:US09859950
申请日:2001-05-21
申请人: Susan Johns
发明人: Susan Johns
IPC分类号: H01L2182
CPC分类号: H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要: The prior art requires the selective removal of antifuse material from the bottom of the standard via. This cannot always be accomplished without damage to the nearby antifuse. In addition, in the absence of antifuse structural isolation, problems were encountered at M2 etch in consistently removing the full thickness of metallic material at this level. Shorting due to underetch was often encountered. These problems were solved by first forming only the antifuse via. This allowed the via to be controlled and optimized for antifuse requirements and for the antifuse material to be patterned without regard to possible side effects on the standard vias. Design rules for overlaps of overfuse and M2 layers were amended such that each antifuse is individually isolated. The latter were then formed, without (as in the prior art) any concerns that the antifuse might be affected. The result is an antifuse that is well isolated from other wiring and a standard via that will facilitate good electrical contact between metal layer 1 and 2.
摘要翻译: 现有技术需要从标准通孔的底部选择性地去除反熔丝材料。 这不能总是在不损坏附近的反熔丝的情况下完成。 此外,在没有反熔丝结构隔离的情况下,在M2蚀刻下遇到的问题是始终如一地去除在该水平的金属材料的全部厚度。 经常遭遇短缺。 首先只形成反熔丝通孔来解决这些问题。 这允许对反熔丝要求进行控制和优化,并且对图案化的反熔丝材料进行控制和优化,而不考虑对标准通孔的可能的副作用。 修改了overfuse和M2层重叠的设计规则,使得每个反熔丝被单独隔离。 然后形成后者(如在现有技术中),任何关于反熔丝可能受到影响的担忧。 结果是与其他布线和标准通孔良好隔离的反熔丝,这将促进金属层1和2之间良好的电接触。
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