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    Memory based on a four-transistor storage cell
    3.
    发明授权
    Memory based on a four-transistor storage cell 有权
    基于四晶体管存储单元的存储器

    公开(公告)号：US06400612B1

    公开(公告)日：2002-06-04

    申请号：US09802715

    申请日：2001-03-08

    申请人： Robert Patti

    发明人： Robert Patti

    IPC分类号： G11C700

    CPC分类号： G11C11/405

    摘要： A memory organized as a two-dimensional array of data storage cells having a plurality of rows and columns. Each data storage cell has first, second, third, and fourth terminals, each data storage cell sinking a current between the first and second terminals indicative of a charge stored therein when the third terminal is at a first potential. The memory has a plurality of bit lines, one corresponding to each column. The first terminal of each data storage cell in each column is connected to the bit line corresponding to that column when the third terminal is at the first potential and each data storage cell is disconnected from that bit line when the third terminal is at a second potential. The memory also includes a plurality of column select lines and row select lines. There is one column select line corresponding to each column and one additional column select line adjacent to either the first or last column. The fourth terminal of each data storage cell in each column is connected to the column select line corresponding to that column. Similarly, there are row select lines, one corresponding to each row, the third terminal of each data storage cell in each row being connected to the row select line corresponding to that row. The second terminal of each data storage cell in each column is connected to the column select line of an adjacent column. The charge stored by each data storage cell is determined by the potential difference between the first and second terminals of that data storage cell when the third and fourth terminals of that data storage cell are held at a first potential.

    摘要翻译： 存储器，其被组织为具有多个行和列的数据存储单元的二维阵列。 每个数据存储单元具有第一，第二，第三和第四端子，当第三端子处于第一电位时，每个数据存储单元吸收指示存储在其中的电荷的第一和第二端子之间的电流。 存储器具有多个位线，一个对应于每列。 当第三终端处于第一电位时，每列中的每个数据存储单元的第一端子连接到与该列相对应的位线，并且当第三端子处于第二电位时，每个数据存储单元与该位线断开连接 。 存储器还包括多个列选择线和行选择线。 对应于每列和一列与第一列或最后一列相邻的附加列选择行，有一列列选择行。 每列中每个数据存储单元的第四个终端连接到与该列对应的列选择行。 类似地，存在行选择线，一行对应于每行，每行中每个数据存储单元的第三端连接到与该行对应的行选择行。 每列中每个数据存储单元的第二个终端连接到相邻列的列选择行。 当数据存储单元的第三和第四端子保持在第一电位时，由每个数据存储单元存储的电荷由该数据存储单元的第一和第二端子之间的电位差决定。

    Bipolar transistor that can be fabricated in CMOS
    4.
    发明授权
    Bipolar transistor that can be fabricated in CMOS 有权
    可以用CMOS制造的双极晶体管

    公开(公告)号：US06300660B1

    公开(公告)日：2001-10-09

    申请号：US09476624

    申请日：1999-12-31

    申请人： Robert Patti

    发明人： Robert Patti

    IPC分类号： H01L2976

    CPC分类号： H01L29/72 ,  H01L27/0738

    摘要： A variable conductance device having a first source region and a first drain region in a semiconductor substrate. A first channel region connects the first source and the first drain regions. A first resistive layer overlies the first channel region and has first and second electrical contacts spaced apart from one another thereon. The conductance of the path between the first source region and the first drain region depends on the current flowing between the first and second electrical contacts. By adding a FET having its gate and source shorted together to the variable conductance device, a device having the current gain characteristics of a bipolar transistor is obtained. The first drain region is connected to the drain of the FET and the source of the FET is connected to the second electrical contact. The precise form of the current transfer function can be altered by connecting a number of variable conductance devices according to the present invention in parallel.

    摘要翻译： 一种在半导体衬底中具有第一源极区域和第一漏极区域的可变电导器件。 第一沟道区域连接第一源极和第一漏极区域。 第一电阻层覆盖在第一沟道区上并具有彼此间隔开的第一和第二电接触。 第一源极区域和第一漏极区域之间的路径的电导取决于在第一和第二电触头之间流动的电流。 通过将其栅极和源极短路的FET添加到可变电导器件，获得具有双极晶体管的电流增益特性的器件。 第一漏区连接到FET的漏极，FET的源极连接到第二电触点。 可以通过并联连接本发明的多个可变电导装置来改变电流传递函数的精确形式。

    Network with programmable interconnect nodes adapted to large integrated circuits
    6.
    发明授权
    Network with programmable interconnect nodes adapted to large integrated circuits 有权
    具有适用于大型集成电路的可编程互连节点的网络

    公开(公告)号：US07159047B2

    公开(公告)日：2007-01-02

    申请号：US10829646

    申请日：2004-04-21

    申请人： Mark Klecka ,  Kamal Khadiri ,  Robert Patti ,  Derrick Brent Wilson ,  Lee Hoyman ,  Bruce Tyda

    发明人： Mark Klecka ,  Kamal Khadiri ,  Robert Patti ,  Derrick Brent Wilson ,  Lee Hoyman ,  Bruce Tyda

    IPC分类号： G06F13/00

    CPC分类号： H04L12/40

    摘要： A circuit having an interconnect network and plurality of processing blocks is disclosed. The interconnect network has a plurality of network nodes arranged in a two-dimensional array on a first substrate. Each network node has a plurality of communication ports and is connected to each adjacent network node by a communication bus that connects only those two network nodes and processing blocks adjacent to that communication bus. A programmable switch within each node connects one of the input ports to one of the output ports in response to connection information stored in a memory in that node. Three-dimensional embodiments can be constructed by including a second substrate that overlies the first substrate and includes a second such interconnect network that is connected vertically through one or more nodes. The circuit easily accommodates spare processing blocks that can be substituted for defective blocks by altering the connection information.

    摘要翻译： 公开了具有互连网络和多个处理块的电路。 互连网络具有在第一基板上以二维阵列布置的多个网络节点。 每个网络节点具有多个通信端口，并且通过仅连接那些两个网络节点和与该通信总线相邻的处理块的通信总线连接到每个相邻的网络节点。 响应于存储在该节点中的存储器中的连接信息，每个节点内的可编程开关将一个输入端口连接到其中一个输出端口。 可以通过包括覆盖在第一衬底上的第二衬底并且包括通过一个或多个节点垂直连接的第二这样的互连网络来构造三维实施例。 该电路容易地容纳可以通过改变连接信息来代替有缺陷的块的备用处理块。

    Four-terminal EEPROM cell for storing an analog voltage and memory system using the same to store multiple bits per EEPROM cell
    9.
    发明授权
    Four-terminal EEPROM cell for storing an analog voltage and memory system using the same to store multiple bits per EEPROM cell 有权

    公开(公告)号：US6154392A

    公开(公告)日：2000-11-28

    申请号：US417040

    申请日：1999-10-12

    申请人： Robert Patti

    发明人： Robert Patti

    IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/28 ,  G11C27/00

    CPC分类号： G11C11/5642 ,  G11C11/5621 ,  G11C11/5628 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/28 ,  G11C27/005 ,  G11C2211/5613 ,  G11C2211/5634

    摘要： A non-volatile memory based on a unique EEPROM memory. The non-volatile memory includes a plurality of data memory cells, a data programming circuit, and a first data line. Each data memory cell includes an EEPROM cell having a separate programming electrode and first and second isolation transistors. The programming electrode is coupled to the floating gate by a tunneling window. The first isolation transistor connects the EEPROM cell to the first data line. The second isolation transistor connects the programming electrode to the data programming circuit in response to a write enable signal. The data programming circuit programs a selected data memory cell by receiving a data value to be stored in that data memory cell and generating and coupling a programming signal to the second isolation transistors, the programming signal having a duration that is determined by the received data value. The memory also includes a plurality of first reference memory cells, a first reference programming circuit, and a first reference line, each first reference memory cell is structurally the same as the data memory cells. There is one first reference memory cell corresponding to each data memory cell, and that first reference cell is programmed with a predetermined value each time the corresponding data memory cell is programmed. A data memory cell is read by comparing the conductance of the first data line to the first reference line. The data reading circuit generates an output value that depends on the compared conductances. In embodiments of the invention using multiple reference cells, the various reference cells are programmed with different fixed values each time the corresponding data memory cell is programmed. The values in these reference cells are interpolated during the reading operation to determine the data value stored in the corresponding data memory cell.