公开(公告)号：US06939815B2

公开(公告)日：2005-09-06

申请号：US10652796

申请日：2003-08-28

申请人： Justin K. Brask ,  Mark L. Doczy ,  Scott A. Hareland ,  John P. Barnak ,  Matthew V. Metz ,  Jack Kavalieros ,  Robert S. Chau

发明人： Justin K. Brask ,  Mark L. Doczy ,  Scott A. Hareland ,  John P. Barnak ,  Matthew V. Metz ,  Jack Kavalieros ,  Robert S. Chau

IPC分类号： H01L21/28 ,  H01L21/30 ,  H01L21/306 ,  H01L21/316 ,  H01L29/51 ,  H01L21/31

CPC分类号： H01L21/02244 ,  H01L21/02052 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28167 ,  H01L21/28194 ,  H01L21/3003 ,  H01L21/31612 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31683 ,  H01L21/31691 ,  H01L29/513 ,  H01L29/517

摘要： A method for making a semiconductor device is described. That method comprises forming a metal oxide layer on a substrate, converting at least part of the metal oxide layer to a metal layer; and oxidizing the metal layer to generate a metal oxide high-k gate dielectric layer.

摘要翻译： 描述制造半导体器件的方法。 该方法包括在基板上形成金属氧化物层，将金属氧化物层的至少一部分转化为金属层; 并氧化金属层以产生金属氧化物高k栅极电介质层。

公开(公告)号：US07217611B2

公开(公告)日：2007-05-15

申请号：US10748383

申请日：2003-12-29

申请人： Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Scott A. Hareland ,  Matthew V. Metz ,  Chris E. Barns ,  Robert S. Chau

发明人： Jack Kavalieros ,  Justin K. Brask ,  Mark L. Doczy ,  Scott A. Hareland ,  Matthew V. Metz ,  Chris E. Barns ,  Robert S. Chau

IPC分类号： H01L21/8238

CPC分类号： H01L29/517 ,  H01L21/823842 ,  H01L29/495 ,  H01L29/66545 ,  Y10S438/926

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods comprise providing a substrate comprising a first transistor structure comprising an n-type gate material and second transistor structure comprising a p-type gate material, selectively removing the n-type gate material to form a recess in the first gate structure, and then filling the recess with an n-type metal gate material.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法包括提供包括包括n型栅极材料的第一晶体管结构和包括p型栅极材料的第二晶体管结构的衬底，选择性地去除n型栅极材料以在第一栅极结构中形成凹陷，然后 用n型金属栅极材料填充凹部。

公开(公告)号：US07101761B2

公开(公告)日：2006-09-05

申请号：US10746323

申请日：2003-12-23

申请人： Robert S. Chau ,  Scott A. Hareland ,  Justin K. Brask ,  Matthew V. Metz

发明人： Robert S. Chau ,  Scott A. Hareland ,  Justin K. Brask ,  Matthew V. Metz

IPC分类号： H01L21/336

CPC分类号： B82Y10/00 ,  G11C2213/17 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0512 ,  Y10S977/848

摘要： A method is described for providing a nanostructure suspended above a substrate surface. The method includes providing a nanostructure encased in an oxide shell on a substrate and depositing a sacrificial material and a support material over the oxide encased nanostructure. Then, the sacrificial material is removed to expose the oxide encased nanostructure. Once the oxide encased nanostructure has been exposed, the oxide shell is removed from the oxide encased nanostructure such that the nanostructure is suspended above the substrate surface.

摘要翻译： 描述了一种用于提供悬浮在衬底表面上方的纳米结构的方法。 该方法包括提供封装在衬底上的氧化物壳中的纳米结构，并在氧化物封装的纳米结构上沉积牺牲材料和载体材料。 然后，去除牺牲材料以暴露氧化物包裹的纳米结构。 一旦氧化物包裹的纳米结构已经暴露，氧化物壳被从氧化物封装的纳米结构中去除，使得纳米结构悬浮在衬底表面上方。

公开(公告)号：US07235809B2

公开(公告)日：2007-06-26

申请号：US11292911

申请日：2005-12-01

申请人： Been-Yih Jin ,  Brian S. Doyle ,  Scott A. Hareland ,  Mark L. Doczy ,  Matthew V. Metz ,  Boyan I. Boyanov ,  Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Been-Yih Jin ,  Brian S. Doyle ,  Scott A. Hareland ,  Mark L. Doczy ,  Matthew V. Metz ,  Boyan I. Boyanov ,  Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L29/06

CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78681

摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.

摘要翻译： 一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。 一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。

公开(公告)号：US07138316B2

公开(公告)日：2006-11-21

申请号：US10669064

申请日：2003-09-23

申请人： Been-Yih Jin ,  Brian S. Doyle ,  Scott A. Hareland ,  Mark L. Doczy ,  Matthew V. Metz ,  Boyan I. Boyanov ,  Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Been-Yih Jin ,  Brian S. Doyle ,  Scott A. Hareland ,  Mark L. Doczy ,  Matthew V. Metz ,  Boyan I. Boyanov ,  Suman Datta ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76886 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78681

摘要： A method including forming a via dielectric layer on a semiconductor device substrate; forming a trench dielectric layer on the via dielectric layer; forming a trench through the trench dielectric layer to expose the via dielectric layer; forming a via in the via dielectric layer through the trench to expose the substrate; and forming a semiconductor material in the via and in the trench. An apparatus including a device substrate; a dielectric layer formed on a surface of the device substrate; and a device base formed on the dielectric layer including a crystalline structure derived from the device substrate.

摘要翻译： 一种包括在半导体器件基板上形成通孔电介质层的方法; 在所述通孔电介质层上形成沟槽电介质层; 通过所述沟槽电介质层形成沟槽以暴露所述通孔电介质层; 在所述通孔电介质层中通过所述沟槽形成通孔以暴露所述衬底; 以及在通孔和沟槽中形成半导体材料。 一种装置，包括：装置基板; 形成在所述器件基板的表面上的电介质层; 以及形成在所述电介质层上的器件基底，其包括衍生自所述器件基板的晶体结构。

公开(公告)号：US07078282B2

公开(公告)日：2006-07-18

申请号：US10749196

申请日：2003-12-30

申请人： Robert S. Chau ,  Justin K. Brask ,  Chris E. Barns ,  Scott A. Hareland

发明人： Robert S. Chau ,  Justin K. Brask ,  Chris E. Barns ,  Scott A. Hareland

IPC分类号： H01L21/338

CPC分类号： H01L29/66545 ,  H01L29/7842

摘要： The present invention relates to the deposition of a layer above a transistor structure, causing crystalline stress within the transistor, and resulting in increased performance. The stress layer may be formed above a plurality of transistors formed on a substrate, or above a plurality of selected transistors.

公开(公告)号：US06787440B2

公开(公告)日：2004-09-07

申请号：US10315268

申请日：2002-12-10

申请人： Christopher G. Parker ,  Markus Kuhn ,  Ying Zhou ,  Scott A. Hareland ,  Suman Datta ,  Nick Lindert ,  Robert S. Chau ,  Timothy E. Glassman ,  Matthew V. Metz ,  Sunit Tyagi

发明人： Christopher G. Parker ,  Markus Kuhn ,  Ying Zhou ,  Scott A. Hareland ,  Suman Datta ,  Nick Lindert ,  Robert S. Chau ,  Timothy E. Glassman ,  Matthew V. Metz ,  Sunit Tyagi

IPC分类号： H01L214763

CPC分类号： H01L21/28194 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/518

摘要： A method for making a semiconductor device is described. That method comprises forming on a substrate a buffer layer and a high-k gate dielectric layer, oxidizing the surface of the high-k gate dielectric layer, and then forming a gate electrode on the oxidized high-k gate dielectric layer.

公开(公告)号：US07326652B2

公开(公告)日：2008-02-05

申请号：US11483295

申请日：2006-07-06

申请人： Robert S. Chau ,  Matthew V. Metz ,  Scott A. Hareland

发明人： Robert S. Chau ,  Matthew V. Metz ,  Scott A. Hareland

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L21/469

CPC分类号： C30B29/22 ,  C30B25/105 ,  C30B25/14 ,  C30B29/16

摘要： An atomic layer deposition process that reduces defective bonds formed when depositing atomic layers on a substrate or atomic layer when forming an integrated circuit device. As the layers are formed, a substrate or previous layer is exposed to a first reactant. After the substrate or layer has reacted with the first reactant, the substrate or layer is exposed to a second reactant. During or after exposure to the second reactant, electromagnetic radiation is applied to the substrate or layer. The electromagnetic radiation excites any defective bonds that may form in the deposition process to an energy level high enough to cause the elements forming the defective bonds to react with other elements contained in the second reactant. The reaction forms desirable bonds which attach to the substrate or previous layer to form an additional new layer.

摘要翻译： 当形成集成电路器件时，原子层沉积工艺可以减少在衬底或原子层上沉积原子层时形成的不良键。 当形成层时，将基底或先前的层暴露于第一反应物。 在衬底或层已经与第一反应物反应之后，衬底或层暴露于第二反应物。 在暴露于第二反应物期间或之后，电磁辐射被施加到基底或层上。 电磁辐射激发在沉积过程中可能形成的任何有缺陷的键，其能级高到足以导致形成缺陷键的元素与包含在第二反应物中的其它元素反应。 该反应形成了附着到基底或先前的层以形成另外的新层的理想的键。

公开(公告)号：US07091129B2

公开(公告)日：2006-08-15

申请号：US10749347

申请日：2003-12-30

申请人： Robert S. Chau ,  Matthew V. Metz ,  Scott A. Hareland

发明人： Robert S. Chau ,  Matthew V. Metz ,  Scott A. Hareland

IPC分类号： H10L21/302 ,  H10L21/461 ,  H10L21/31 ,  H10L21/469

CPC分类号： C30B29/22 ,  C30B25/105 ,  C30B25/14 ,  C30B29/16

摘要： An atomic layer deposition process that reduces defective bonds formed when depositing atomic layers on a substrate or atomic layer when forming an integrated circuit device. As the layers are formed, a substrate or previous layer is exposed to a first reactant. After the substrate or layer has reacted with the first reactant, the substrate or layer is exposed to a second reactant. During or after exposure to the second reactant, electromagnetic radiation is applied to the substrate or layer. The electromagnetic radiation excites any defective bonds that may form in the deposition process to an energy level high enough to cause the elements forming the defective bonds to react with other elements contained in the second reactant. The reaction forms desirable bonds which attach to the substrate or previous layer to form an additional new layer.

公开(公告)号：US07018549B2

公开(公告)日：2006-03-28

申请号：US10748617

申请日：2003-12-29

申请人： Matthew V. Metz ,  Scott A. Hareland ,  Robert S. Chau

发明人： Matthew V. Metz ,  Scott A. Hareland ,  Robert S. Chau

IPC分类号： B82B3/00

CPC分类号： B22F1/0025 ,  B22F1/0018 ,  B22F2998/00 ,  B22F2999/00 ,  B82Y30/00 ,  Y10S977/762 ,  Y10T117/10 ,  B22F1/004 ,  B22F9/16

摘要： A method is described for fabricating multiple nanowires of uniform length from a single precursor nucleation particle. The method includes growing a first nanowire segment from a nanoparticle and growing a second nanowire segment between the first nanowire segment and the nanoparticle. The first nanowire segment and the second nanowire segment have a different solubility.

摘要翻译： 描述了从单个前体成核颗粒制造具有均匀长度的多个纳米线的方法。 该方法包括从纳米颗粒生长第一纳米线段并在第一纳米线段和纳米颗粒之间生长第二纳米线段。 第一纳米线段和第二纳米线段具有不同的溶解度。