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1.发明授权Method for use in brazing an interconnect pin to a metallization pattern situated on a brittle dielectric substrate 失效用于将互连针钎焊到位于脆性电介质基底上的金属化图案的方法
公开(公告)号：US4672739A
公开(公告)日：1987-06-16
申请号：US721885
申请日：1985-04-11
CPC分类号： H01L21/4853 , Y10T29/49149 , Y10T428/12542
摘要： A method for use in brazing an interconnect pin to a portion of metallization pattern (e.g. a pad) existing on a brittle dielectric substrate, such as a multi-layered ceramic (MLC) substrate, is disclosed. A dielectric layer is formed with appropriate annular openings. Each opening provides a closed containment wall, which extends around and above the pad, to hold the brazing alloy. Each circular containment wall is concentrically aligned with its associated pad and exposes an area, of each pad, having a smaller diameter than that of the entire pad. The containment walls serve to prevent the brazing alloy from coming into contact with any edge of the pads.
摘要翻译： 公开了一种用于将互连销钎焊到存在于脆性电介质基板（例如多层陶瓷（MLC）基板）上的金属化图案（例如，焊盘）的一部分的方法。 电介质层由合适的环形开口形成。 每个开口提供封闭的容纳壁，其围绕和移动焊盘延伸以保持钎焊合金。 每个圆形容纳壁与其相关联的垫同心地对齐，并且暴露每个垫的面积小于整个垫的直径的区域。 容纳壁用于防止钎焊合金与焊盘的任何边缘接触。
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2.发明授权Apparatus for providing an electrical connection to a metallic pad situated on a brittle dielectric substrate 失效用于向位于脆性电介质基片上的金属焊盘提供电连接的装置
公开(公告)号：US4755631A
公开(公告)日：1988-07-05
申请号：US27865
申请日：1987-03-19
CPC分类号： H01L21/4853 , Y10T29/49144 , Y10T29/49149 , Y10T428/12542
摘要： Apparatus is described for providing an electrical connection to a metallic pad situated on a brittle dielectric substrate, such as a multi-layered ceramic (MLC) substrate, that reduces tensile stress occurring between the pad and the substrate.
摘要翻译： 描述了用于提供与位于诸如多层陶瓷（MLC）基片之类的脆性电介质基底上的金属垫的电连接的装置，该多层陶瓷（MLC）衬底减小了衬垫和衬底之间产生的拉应力。
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公开(公告)号：US06746933B1
公开(公告)日：2004-06-08
申请号：US09999803
申请日：2001-10-26
申请人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
发明人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
IPC分类号： H01L21762
CPC分类号： H01L21/76224
摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.
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公开(公告)号：US06333531B1
公开(公告)日：2001-12-25
申请号：US09239655
申请日：1999-01-29
申请人： Yun-Yu Wang , Johnathan E. Faltermeier , Philip L. Flaitz , Jeffery L. Hurd , Rajarao Jammy , Radhika Srinivasan , Francis G. Trudeau , Dinah S. Weiss
发明人： Yun-Yu Wang , Johnathan E. Faltermeier , Philip L. Flaitz , Jeffery L. Hurd , Rajarao Jammy , Radhika Srinivasan , Francis G. Trudeau , Dinah S. Weiss
IPC分类号： H01L27108
CPC分类号： H01L27/10867
摘要： A process for forming a small grain structure in a material within a semiconductor device near the interface of an adjacent dissimilar material, to result in a highly diffusive grain structure. The highly diffusive grain structure formed within one material enhances diffusion of a dopant impurity, and provides for improved dopant control in an adjacent dissimilar material.
摘要翻译： 在邻近异种材料的界面附近的半导体器件内的材料中形成小晶粒结构的工艺，导致高扩散晶粒结构。 在一种材料内部形成的高度扩散的晶粒结构增强了掺杂杂质的扩散，并提供了在相邻不同材料中的改进的掺杂剂控制。
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5.发明申请STRUCTURE TO IMPROVE ADHESION BETWEEN TOP CVD LOW-K DIELECTRIC AND DIELECTRIC CAPPING LAYER 有权结构提高顶级CVD低K电介质和介电吸收层之间的粘合力公开(公告)号：US20080254643A1
公开(公告)日：2008-10-16
申请号：US12143917
申请日：2008-06-23
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Darren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Darren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L21/768
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。
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6.发明授权Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer 有权结构以改善顶部CVD低介电常数介电层和电介质顶盖层之间的附着力公开(公告)号：US07402532B2
公开(公告)日：2008-07-22
申请号：US11499220
申请日：2006-08-04
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L23/48
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx- or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。
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7.发明授权公开(公告)号：US06960514B2
公开(公告)日：2005-11-01
申请号：US10803395
申请日：2004-03-18
申请人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
发明人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.
摘要翻译： 对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。 投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。 还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部 区域结构。 本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。
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8.发明授权
公开(公告)号：US5167913A
公开(公告)日：1992-12-01
申请号：US813244
申请日：1991-12-23
申请人： John Acocella , Philip L. Flaitz , Raj N. Master , Chandrasekhar Narayan , Sarah H. Knickerbocker , Paul H. Palmateer , Sampath Purushothaman , Srinivasa S. N. Reddy
发明人： John Acocella , Philip L. Flaitz , Raj N. Master , Chandrasekhar Narayan , Sarah H. Knickerbocker , Paul H. Palmateer , Sampath Purushothaman , Srinivasa S. N. Reddy
CPC分类号： H05K3/1291 , H01L21/4846 , H01L21/486 , H05K1/092 , H05K2203/1126 , H05K3/4629 , Y10T428/12528 , Y10T428/12611
摘要： A method of forming an adherent layer of metallurgy on a ceramic substrate which includes the steps of obtaining a ceramic material containing a polymeric binder and copper metallurgy patterns within the ceramic body. In one embodiment of the invention, the ceramic body also contains MgO.Thereafter, a surface layer of metallurgy is formed on the surface of the ceramic body. In one embodiment, the surface layer is nickel and in another embodiment, the surface layer is copper or gold.Then, the ceramic body undergoes a sintering cycle which includes the steps of pyrolysis, binder burnoff and, lastly, densification and, in some cases, crystallization. During densification and crystallization, there is a predetermined steam atmosphere which meets the following requirements: a partial pressure of oxygen less than that necessary to satisfy the equilibrium equation 4Cu+O.sub.2 =2Cu.sub.2 O; and a partial pressure of oxygen less than or equal to that necessary to satisfy the equilibrium equation 2Ni+O.sub.2 =2NiO for nickel in said surface metallurgy.
摘要翻译： 一种在陶瓷基板上形成冶金粘附层的方法，包括以下步骤：在陶瓷体内获得含有聚合物粘合剂和铜冶金图案的陶瓷材料。 在本发明的一个实施例中，陶瓷体还含有MgO。 此后，在陶瓷体的表面上形成表面冶金层。 在一个实施方案中，表面层是镍，在另一个实施方案中，表面层是铜或金。 然后，陶瓷体经历烧结循环，其包括热解，粘合剂燃烧的步骤，最后是致密化，在某些情况下，结晶。 在致密化和结晶过程中，有一个预定的蒸气气氛满足以下要求：氧气分压小于满足平衡方程式4Cu + O2 = 2Cu2O所需的氧分压; 以及小于或等于满足所述表面冶金中镍的平衡方程式2Ni + O2 = 2NiO所需的氧分压。
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9.发明授权Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer 有权结构以改善顶部CVD低介电常数介电层和电介质顶盖层之间的附着力公开(公告)号：US07102232B2
公开(公告)日：2006-09-05
申请号：US10827693
申请日：2004-04-19
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译： 一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合 通过在两个电介质层之间引入粘附过渡层来改善N和H。 在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。 本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。 还提供了形成这种结构，特别是粘附过渡层的方法。
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公开(公告)号：US06740568B2
公开(公告)日：2004-05-25
申请号：US10206875
申请日：2002-07-29
申请人： Yun Yu Wang , Johnathan Faltermeier , Colleen M. Snavely , Michael Maldei , Michael M. Iwatake , David M. Dobuzinsky , Ravikumar Ramachandran , Viraj Y. Sardesai , Philip L. Flaitz , Lisa Y. Ninomiya
发明人： Yun Yu Wang , Johnathan Faltermeier , Colleen M. Snavely , Michael Maldei , Michael M. Iwatake , David M. Dobuzinsky , Ravikumar Ramachandran , Viraj Y. Sardesai , Philip L. Flaitz , Lisa Y. Ninomiya
IPC分类号： H01L2136
CPC分类号： H01L21/02667 , H01L21/02046 , H01L21/02532 , H01L21/2022 , H01L21/28525 , H01L27/10873
摘要： In a method of forming a contact, a liner reactive ion etch is affected on a substrate to remove silicon nitride and silicon oxide. An oxygen plasma ex-situ clean, a Huang AB clean, and a dilute hydrofluric acid (DHF) clean are affected. Amorphous silicon is deposited and an anneal is performed to regrow and recrystallize amorphous silicon.
摘要翻译： 在形成接触的方法中，在衬底上影响衬里反应离子蚀刻以去除氮化硅和氧化硅。 氧等离子体原位清洗，黄AB清洁剂和稀释的氢氟酸（DHF）清洁剂都受到影响。 沉积非晶硅并进行退火以再结晶并重结晶非晶硅。
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