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    Semiconductor memory device and method of operation thereof
    1.
    发明授权
    Semiconductor memory device and method of operation thereof 失效
    半导体存储器件及其操作方法

    公开(公告)号：US5629888A

    公开(公告)日：1997-05-13

    申请号：US182503

    申请日：1994-01-18

    申请人： Ryuichi Saito ,  Hidekatsu Onose ,  Yutaka Kobayashi ,  Michio Ohue

    发明人： Ryuichi Saito ,  Hidekatsu Onose ,  Yutaka Kobayashi ,  Michio Ohue

    IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C11/56 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112 ,  H01L27/115

    CPC分类号： H01L27/11502 ,  G11C11/22 ,  G11C11/5657 ,  G11C16/08 ,  G11C8/14 ,  H01L27/10805

    摘要： A semiconductor memory device has a plurality of memory cells in an array, into which the memory cells data is writable, and which can subsequently be read. Each memory cell has a switching element with one terminal connected to a bit line of the array another terminal connected to at least one ferroelectric capacitor, and a control terminal connected to a word line. The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor and a capacitor other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.

    摘要翻译： 半导体存储器件具有阵列中的多个存储器单元，存储器单元数据可写入其中，并且随后可以读取存储单元。 每个存储单元具有开关元件，一个端子连接到阵列的位线，另一个端子连接到至少一个铁电电容器，以及控制端子连接到字线。 然后可以操作电池以在施加电压时检测铁电电容器的极化变化，这不足以引起铁电电容器的状态改变。 或者，铁电电容器和除铁电电容器之外的电容器连接到开关元件。 在另一替代方案中，多个铁电电容器连接到开关元件，使得不同的数据可写入每个。

    Semiconductor memory device and methods of operation thereof
    2.
    发明授权
    Semiconductor memory device and methods of operation thereof 失效
    半导体存储器件及其操作方法

    公开(公告)号：US06940741B2

    公开(公告)日：2005-09-06

    申请号：US10807272

    申请日：2004-03-24

    申请人： Ryuichi Saito ,  Hidekatsu Onose ,  Yutaka Kobayashi ,  Michio Ohue

    发明人： Ryuichi Saito ,  Hidekatsu Onose ,  Yutaka Kobayashi ,  Michio Ohue

    IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C11/56 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112 ,  H01L27/115 ,  G11C11/24

    CPC分类号： H01L27/11502 ,  G11C8/14 ,  G11C11/22 ,  G11C11/5657 ,  G11C16/08 ,  H01L27/10805

    摘要： A semiconductor memory device has a plurality of memory cells in an array, into which the memory cells data is writable, and which can subsequently be read. Each memory cell has a switching element with one terminal connected to a bit line of the array another terminal connected to at least one ferroelectric capacitor, and a control terminal connected to a word line. The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor and a capacitor other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.

    摘要翻译： 半导体存储器件具有阵列中的多个存储器单元，存储器单元数据可写入其中，并且随后可以读取存储单元。 每个存储单元具有开关元件，一个端子连接到阵列的位线，另一个端子连接到至少一个铁电电容器，以及控制端子连接到字线。 然后可以操作电池以在施加电压时检测铁电电容器的极化变化，这不足以引起铁电电容器的状态改变。 或者，铁电电容器和除铁电电容器之外的电容器连接到开关元件。 在另一替代方案中，多个铁电电容器连接到开关元件，使得不同的数据可写入每个。

    Semiconductor memory device and method of operation thereof
    3.
    发明授权
    Semiconductor memory device and method of operation thereof 失效
    半导体存储器件及其操作方法

    公开(公告)号：US5307304A

    公开(公告)日：1994-04-26

    申请号：US738601

    申请日：1991-07-31

    申请人： Ryuichi Saito ,  Hidekatsu Onose ,  Yutaka Kobayashi ,  Michio Ohue

    发明人： Ryuichi Saito ,  Hidekatsu Onose ,  Yutaka Kobayashi ,  Michio Ohue

    IPC分类号： G11C14/00 ,  G11C11/22 ,  G11C11/56 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112 ,  H01L27/115

    CPC分类号： H01L27/11502 ,  G11C11/22 ,  G11C11/5657 ,  G11C16/08 ,  G11C8/14 ,  H01L27/10805

    摘要： A semiconductor memory device has a plurality of memory cells in an array, into which the memory cells data is writable, and which can subsequently be read. Each memory cell has a switching element with one terminal connected to a bit line of the array another terminal connected to at least one ferroelectric capacitor, and a control terminal connected to a word line. The cell may then be operated to detect the change in polarization of the ferroelectric capacitor when a voltage is applied which is not sufficient to cause a change of state of the ferroelectric capacitor. Alternatively, a ferroelectric capacitor and a capacitor other than a ferroelectric capacitor is connected to the switching element. In a further alternative, a plurality of ferroelectric capacitors are connected to the switching element, so that different data are writable into each.

    摘要翻译： 半导体存储器件具有阵列中的多个存储器单元，存储器单元数据可写入其中，并且随后可以读取存储单元。 每个存储单元具有开关元件，一个端子连接到阵列的位线，另一个端子连接到至少一个铁电电容器，以及控制端子连接到字线。 然后可以操作电池以在施加电压时检测铁电电容器的极化变化，这不足以引起铁电电容器的状态改变。 或者，铁电电容器和除铁电电容器之外的电容器连接到开关元件。 在另一替代方案中，多个铁电电容器连接到开关元件，使得不同的数据可写入每个。

    BIPOLAR DEVICE AND FABRICATION METHOD THEREOF
    7.
    发明申请
    BIPOLAR DEVICE AND FABRICATION METHOD THEREOF 有权
    双极器件及其制造方法

    公开(公告)号：US20090057685A1

    公开(公告)日：2009-03-05

    申请号：US12176635

    申请日：2008-07-21

    申请人： Kazuhiro MOCHIZUKI ,  Hidekatsu Onose ,  Natsuki Yokoyama

    发明人： Kazuhiro MOCHIZUKI ,  Hidekatsu Onose ,  Natsuki Yokoyama

    IPC分类号： H01L29/24

    CPC分类号： H01L29/1608 ,  H01L29/0804 ,  H01L29/66068 ,  H01L29/7322

    摘要： In a mesa type bipolar transistor or a thyristor, since carriers injected from an emitter layer or an anode layer to a base layer or a gate layer diffuse laterally and are recombined, reduction in the size and improvement for the switching frequency is difficult.In the invention, the emitter layer or the anode layer is formed of two high-doped and low-doped layers, a semiconductor region for suppressing recombination comprising an identical semiconductor having an impurity density identical with that of the low-doped layer is present being in contact with a base layer or a gate layer and a surface passivation layer, and the width of the semiconductor region for suppressing recombination is defined equal with or longer than the diffusion length of the carrier. This provides an effect of attaining reduction in the size of the bipolar transistor or improvement of the switching frequency of the thyristor without deteriorating the performance. Further, this has an effect of greatly improving the current gain by successively stacking above the high-doped emitter layer of the bipolar transistor, a hole barrier layer, a conduction band discontinuity relaxed layer and an emitter contact layer.

    摘要翻译： 在台式双极晶体管或晶闸管中，由于从发射极层或阳极层向基极层或栅极层注入的载流子横向漫射并重新组合，因此难以减小开关频率的尺寸和改善。 在本发明中，发射极层或阳极层由两个高掺杂和低掺杂层形成，用于抑制复合的半导体区域包括具有与低掺杂层的杂质密度相同的杂质密度的相同半导体， 与基底层或栅极层和表面钝化层接触，并且用于抑制复合的半导体区域的宽度被限定为等于或长于载体的扩散长度。 这提供了在不降低性能的情况下实现双极晶体管的尺寸的减小或晶闸管的开关频率的提高的效果。 此外，这具有通过连续堆叠在双极晶体管，空穴阻挡层，导带不连续松弛层和发射极接触层的高掺杂发射极层上方大大改善电流增益的效果。

    Static induction transistor
    8.
    发明授权
    Static induction transistor 失效
    静电感应晶体管

    公开(公告)号：US06750477B2

    公开(公告)日：2004-06-15

    申请号：US10121623

    申请日：2002-04-15

    申请人： Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Hidekatsu Onose ,  Saburo Oikawa

    发明人： Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Hidekatsu Onose ,  Saburo Oikawa

    IPC分类号： H01L310312

    CPC分类号： H01L29/7722 ,  H01L29/1608

    摘要： In a static induction transistor, in addition to a first gate layer (4), a plurality of second gate layers (41) having a shallower depth and a narrower gap therebetween than those of the first gate layer (4) are provided in an area surrounded by the first gate layer (4), thereby an SiC static induction transistor with an excellent off characteristic is realized, while ensuring a required processing accuracy during production thereof.

    摘要翻译： 在静电感应晶体管中，除了第一栅极层（4）之外，还具有与第一栅极层（4）相比具有较浅深度和间隔更窄的多个第二栅极层（41） 由第一栅极层（4）包围，从而实现具有优异的截止特性的SiC静态感应晶体管，同时确保其制造期间所需的加工精度。

    Semiconductor device and power converter using the same
    9.
    发明授权
    Semiconductor device and power converter using the same 失效
    半导体器件和功率转换器使用相同

    公开(公告)号：US06566726B1

    公开(公告)日：2003-05-20

    申请号：US09516501

    申请日：2000-03-01

    申请人： Hidekatsu Onose ,  Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Saburou Oikawa

    发明人： Hidekatsu Onose ,  Tsutomu Yatsuo ,  Toshiyuki Ohno ,  Saburou Oikawa

    IPC分类号： H01L2940

    CPC分类号： H01L29/0615 ,  H02M7/003

    摘要： To reduce the field intensity on the termination surface, almost not affecting the on-characteristic, a drift layer is made of two layers, an n-layer and n− layer, and a termination region is formed on the surface of the above n− layer. An impurity concentration ratio between the n− layer and the n-layer is less than 1:2, and the thickness of the n− layer is less than that of a source n+ layer. Reliability can be secured even in a high temperature operation.

    摘要翻译： 为了降低终端表面上的场强，几乎不影响导通特性，漂移层由n层和n层两层构成，并且在上述n-层的表面上形成端接区， 层。 n层和n层之间的杂质浓度比小于1：2，n层的厚度小于源n +层的厚度。 即使在高温操作中也可以确保可靠性。

    Semiconductor device and package structure therefore and power inverter having semiconductor device
    10.
    发明授权
    Semiconductor device and package structure therefore and power inverter having semiconductor device 失效
    因此，半导体器件和封装结构以及具有半导体器件的功率逆变器

    公开(公告)号：US5652467A

    公开(公告)日：1997-07-29

    申请号：US507989

    申请日：1995-07-27

    申请人： Hidekatsu Onose ,  Shuroku Sakurada

    发明人： Hidekatsu Onose ,  Shuroku Sakurada

    IPC分类号： H01L23/48

    CPC分类号： H01L24/72 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01082 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/30107

    摘要： An auxiliary cathode lead is contacted to a cathode buffer electrode which contacts to an unit GTO arranged at the most remote region from a gate pressure contacting portion of a GTO pellet and the push-into effect of the auxiliary cathode current during the turn-off can be remarkably performed. Without inviting bad affects such as the increase in "on" voltage, it is proposed a package structure of a semiconductor which the unit GTO arranged remote from a gate is easily to perform the turn-off. The maximum turn-off current can be heightened, it can easily correspond to the increase in the diameter of the pellet according to the large current of the unit element. Further, a condenser of a snubber circuit as a protection circuit of the unit GTO in a power inverter can be small, and the snubber loss can be lessened.

    摘要翻译： 辅助阴极引线与阴极缓冲电极接触，该阴极缓冲电极与GTO颗粒的栅极压力接触部分最远的区域布置的单元GTO接触，并且关断期间辅助阴极电流的推入效应 被显着地执行。 没有引起诸如“开”电压增加的不良影响，提出了一种半导体的封装结构，其中远离栅极的单元GTO易于执行关断。 可以提高最大关断电流，可以根据单元元件的大电流容易地对应于颗粒的直径的增加。 此外，作为功率逆变器中的单元GTO的保护电路的缓冲电路的电容器可以很小，并且可以减小缓冲器损耗。