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公开(公告)号：US09155192B2
公开(公告)日：2015-10-06
申请号：US14051019
申请日：2013-10-10
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Kyung Ho Lee , Seung Wan Woo , Po Chul Kim , Young Nam Hwang , Suk Jin Ham
CPC classification number: H05K1/0271 , H01L23/06 , H01L23/16 , H01L23/3171 , H01L23/562 , H01L2924/0002 , H01L2924/3511 , H05K3/285 , H05K3/3431 , H05K2201/0175 , H05K2201/0191 , H05K2201/068 , H05K2203/1327 , H01L2924/00
Abstract: Disclosed herein is an electronic component package including: a connection member provided on at least one surface of a substrate; an active element coupled to the substrate by the connection member; a molding part covering an exposed surface of the active element; and an additional layer formed on an exposed surface of the molding part to decrease a warpage phenomenon. In the electronic component package, the warpage phenomenon may be decreased as compared with the related art.
Abstract translation: 本文公开了一种电子部件封装，包括：设置在基板的至少一个表面上的连接部件; 通过所述连接部件与所述基板连接的有源元件; 覆盖有源元件的暴露表面的成型部件; 以及形成在模制部件的暴露表面上的附加层，以减少翘曲现象。 在电子部件封装中，与现有技术相比，翘曲现象可能会降低。
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公开(公告)号：US09171780B2
公开(公告)日：2015-10-27
申请号：US14527733
申请日：2014-10-29
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Yee Na Shin , Young Nam Hwang , Hyun Bok Kwon , Seung Wan Woo
CPC classification number: H01L21/561 , H01L21/288 , H01L21/565 , H01L21/568 , H01L21/76802 , H01L21/76879 , H01L21/78 , H01L23/3128 , H01L23/481 , H01L23/544 , H01L24/11 , H01L24/19 , H01L24/27 , H01L24/96 , H01L24/97 , H01L2223/54426 , H01L2223/54486 , H01L2224/12105 , H01L2224/14 , H01L2924/12042 , H01L2924/181 , H01L2924/00
Abstract: Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip.
Abstract translation: 本文公开了一种半导体封装的制造方法。 根据本发明的优选实施例，一种制造半导体封装的方法包括：制备具有多个四边形孔的矩形框架; 将多个半导体芯片和框架附接在磁带的一个表面上; 在所述带上形成模制部件以覆盖所述半导体芯片和所述框架; 剥皮; 在剥离的部分形成树脂层; 并在与半导体芯片连接的树脂层上形成布线。
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公开(公告)号：US20150147849A1
公开(公告)日：2015-05-28
申请号：US14527733
申请日：2014-10-29
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Yee Na SHIN , Young Nam Hwang , Hyun Bok Kwon , Seung Wan Woo
CPC classification number: H01L21/561 , H01L21/288 , H01L21/565 , H01L21/568 , H01L21/76802 , H01L21/76879 , H01L21/78 , H01L23/3128 , H01L23/481 , H01L23/544 , H01L24/11 , H01L24/19 , H01L24/27 , H01L24/96 , H01L24/97 , H01L2223/54426 , H01L2223/54486 , H01L2224/12105 , H01L2224/14 , H01L2924/12042 , H01L2924/181 , H01L2924/00
Abstract: Disclosed herein is a method for manufacturing a semiconductor package. According to a preferred embodiment of the present invention, a method for manufacturing a semiconductor package includes: preparing a rectangular frame having a plurality of quadrangular holes; attaching a plurality of semiconductor chips and the frame on one surface of a tape; forming a molding part on the tape to cover the semiconductor chip and the frame; peeling the tape; forming a resin layer at a portion at which the tape is peeled; and forming a wiring on the resin layer to be connected to the semiconductor chip.0
Abstract translation: 本文公开了一种半导体封装的制造方法。 根据本发明的优选实施例，一种制造半导体封装的方法包括：制备具有多个四边形孔的矩形框架; 将多个半导体芯片和框架附接在磁带的一个表面上; 在所述带上形成模制部件以覆盖所述半导体芯片和所述框架; 剥皮; 在剥离的部分形成树脂层; 并在与半导体芯片连接的树脂层上形成布线
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公开(公告)号：US20140374870A1
公开(公告)日：2014-12-25
申请号：US14170325
申请日：2014-01-31
Applicant: Samsung Electro-Mechanics Co., Ltd.
Inventor： Kyung Ho Lee , Suk Jin Ham , Seung Wan Woo , Yee Na Shin
IPC: H01L27/146
CPC classification number: H01L27/14618 , H01L25/041 , H01L25/105 , H01L27/14625 , H01L27/14632 , H01L27/14687 , H01L2924/0002 , H01L2924/00
Abstract: Disclosed herein are an image sensor module and a method of manufacturing the same. The image sensor includes: a base substrate having an image sensor mounted groove including a first groove and a second groove having a stepped shape; and an image sensor mounted in a groove of the base substrate.
Abstract translation: 这里公开了图像传感器模块及其制造方法。 图像传感器包括：基底，具有安装有图像传感器的凹槽，该凹槽包括第一凹槽和具有台阶形状的第二凹槽; 以及安装在基底基板的凹槽中的图像传感器。
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5.发明授权Printed circuit board having embedded electronic device and method of manufacturing the same 有权具有嵌入式电子装置的印刷电路板及其制造方法公开(公告)号：US09504169B2
公开(公告)日：2016-11-22
申请号：US14060365
申请日：2013-10-22
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Young Nam Hwang , Ju Wan Nam , Seung Wan Woo , Yee Na Shin
CPC classification number: H05K3/4697 , H01L24/19 , H01L2224/04105 , H05K1/185 , H05K3/0032 , H05K3/4602 , H05K3/4652 , H05K2201/09827 , Y10T29/4913 , Y10T29/49146
Abstract: Disclosed herein are a printed circuit board having an embedded electronic device and a method of manufacturing the same. According to a preferred embodiment of the present invention, the printed circuit board having an embedded electronic device includes: a core substrate having circuit layers formed on both surfaces thereof; a taper-shaped cavity formed on the core substrate; and an electronic device embedded in the cavity.
Abstract translation: 这里公开了具有嵌入式电子装置的印刷电路板及其制造方法。 根据本发明的优选实施例，具有嵌入式电子设备的印刷电路板包括：具有形成在其两个表面上的电路层的芯基板; 形成在芯基板上的锥形空腔; 以及嵌入腔内的电子装置。
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Patent Agency Ranking
公开(公告)号：US09470635B2
公开(公告)日：2016-10-18
申请号：US14048703
申请日：2013-10-08
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD
Inventor： Seung Wan Woo , Young Nam Hwang , Po Chul Kim , Kyung Ho Lee , Suk Jin Ham
CPC classification number: G01N21/88 , G01B11/306 , G01N25/16
Abstract: Disclosed herein are a system of measuring a warpage and a method of measuring a warpage. The system of measuring a warpage of a sample by analyzing an image photographed by the camera using light that is diffused from a light source and reflected on a surface of a sample and is arrived at the camera through a reference grating part, the system includes: an intake part that removes a fume generated from the sample. By this configuration, it is possible to measure the warpage while effectively removing the fume generated from the sample according to the increase in the temperature of the sample at the time of measuring the warpage, thereby improving the accuracy of the warpage measurement.
Abstract translation: 这里公开了测量翘曲的系统和测量翘曲的方法。 通过使用从光源扩散并在样品表面上反射的光通过分析由相机拍摄的图像并通过参考光栅部件到达相机的方式来测量样品的翘曲的系统，该系统包括： 一个摄取部分去除样品产生的烟雾。 通过该结构，可以根据测定翘曲时的试样的温度的上升而有效地除去样品产生的烟雾，能够测量翘曲，提高翘曲测定精度。
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7.发明申请PRINTED CIRCUIT BOARD HAVING EMBEDDED ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME 有权具有嵌入式电子设备的印刷电路板及其制造方法公开(公告)号：US20150014034A1
公开(公告)日：2015-01-15
申请号：US14060365
申请日：2013-10-22
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Young Nam Hwang , Ju Wan Nam , Seung Wan Woo , Yee Na Shin
CPC classification number: H05K3/4697 , H01L24/19 , H01L2224/04105 , H05K1/185 , H05K3/0032 , H05K3/4602 , H05K3/4652 , H05K2201/09827 , Y10T29/4913 , Y10T29/49146
Abstract: Disclosed herein are a printed circuit board having an embedded electronic device and a method of manufacturing the same. According to a preferred embodiment of the present invention, the printed circuit board having an embedded electronic device includes: a core substrate having circuit layers formed on both surfaces thereof; a taper-shaped cavity formed on the core substrate; and an electronic device embedded in the cavity.
Abstract translation: 这里公开了具有嵌入式电子装置的印刷电路板及其制造方法。 根据本发明的优选实施例，具有嵌入式电子设备的印刷电路板包括：具有形成在其两个表面上的电路层的芯基板; 形成在芯基板上的锥形空腔; 以及嵌入腔内的电子装置。
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8.发明申请CALIBRATION BLOCK FOR MEASURING WARPAGE, WARPAGE MEASURING APPARATUS USING THE SAME, AND METHOD THEREOF 审中-公开用于测量温度的校准块，使用其的温度测量装置及其方法公开(公告)号：US20140354797A1
公开(公告)日：2014-12-04
申请号：US14182186
申请日：2014-02-17
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Seung Wan Woo , Ju Wan Nam , Young Nam Hwang , Kyung Ho Lee , Suk Jin Ham
CPC classification number: G01B11/254 , G01B11/2504 , G01B11/306 , G01B2210/56
Abstract: Disclosed herein are a calibration block for measuring warpage, a warpage measuring apparatus using the same, and a method thereof. The calibration block includes a substrate having one planar surface; and a stepped part forming a step at the center of the other surface of the substrate.
Abstract translation: 本文公开了一种用于测量翘曲的校准块，使用其的翘曲测量装置及其方法。 校准块包括具有一个平面的衬底; 以及在基板的另一个表面的中心形成台阶的台阶部。
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公开(公告)号：US20140146498A1
公开(公告)日：2014-05-29
申请号：US14051019
申请日：2013-10-10
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Kyung Ho Lee , Seung Wan Woo , Po Chul Kim , Young Nam Hwang , Suk Jin Ham
IPC: H05K1/02
CPC classification number: H05K1/0271 , H01L23/06 , H01L23/16 , H01L23/3171 , H01L23/562 , H01L2924/0002 , H01L2924/3511 , H05K3/285 , H05K3/3431 , H05K2201/0175 , H05K2201/0191 , H05K2201/068 , H05K2203/1327 , H01L2924/00
Abstract: Disclosed herein is an electronic component package including: a connection member provided on at least one surface of a substrate; an active element coupled to the substrate by the connection member; a molding part covering an exposed surface of the active element; and an additional layer formed on an exposed surface of the molding part to decrease a warpage phenomenon. In the electronic component package, the warpage phenomenon may be decreased as compared with the related art.
Abstract translation: 本文公开了一种电子部件封装，包括：设置在基板的至少一个表面上的连接部件; 通过所述连接部件与所述基板连接的有源元件; 覆盖有源元件的暴露表面的成型部件; 以及形成在模制部件的暴露表面上的附加层，以减少翘曲现象。 在电子部件封装中，与现有技术相比，翘曲现象可能会降低。
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公开(公告)号：US20140061891A1
公开(公告)日：2014-03-06
申请号：US13800662
申请日：2013-03-13
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Po Chul KIM , Kyung Ho Lee , Seung Wan Woo , Young Nam Hwang , Suk Jin Ham
CPC classification number: H01L23/562 , H01L21/56 , H01L21/565 , H01L23/3121 , H01L2224/48227 , H01L2924/3511
Abstract: Disclosed herein are a semiconductor chip package and a manufacturing method thereof. The manufacturing method of the semiconductor chip package includes: a) mounting a semiconductor chip on a printed circuit board (PCB); b) inserting a warpage suppressing reinforcement member into an inner ceiling of a mold manufactured in order to package the PCB having the semiconductor chip mounted thereon; c) combining the mold having the warpage suppressing reinforcement member inserted into the ceiling thereof with the upper surface of the PCB so as to surround the PCB having the semiconductor chip mounted thereon; d) injection-molding and filling a molding material in the mold, and hardening the molding material by applying heat, and e) hardening the molding material and then removing the mold to complete the semiconductor chip package.
Abstract translation: 本文公开了一种半导体芯片封装及其制造方法。 半导体芯片封装的制造方法包括：a）将半导体芯片安装在印刷电路板（PCB）上; b）将翘曲抑制加强构件插入制造的模具的内部天花板中，以便封装其上安装有半导体芯片的PCB; c）将插入其天花板的具有翘曲抑制加强件的模具与PCB的上表面结合，以便围绕安装有半导体芯片的PCB; d）在模具中注射成型并填充模塑材料，并通过加热来硬化模塑材料，以及e）硬化模制材料，然后移除模具以完成半导体芯片封装。
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