公开(公告)号：US20210384100A1

公开(公告)日：2021-12-09

申请号：US17307181

申请日：2021-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Chang RYU ,  Chulwoo KIM ,  Juhyun LYU ,  Sanghyun LEE ,  Yun Seok CHOI

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor package includes a first substrate, a first chip structure and a second chip structure spaced apart from each other on the first substrate, a gap region being defined between the first and second chip structures, and a heat dissipation member covering the first chip structure, the second chip structure, and the first substrate, the heat dissipation member including a first trench in an inner top surface of the heat dissipation member, wherein the first trench vertically overlaps with the gap region and has a width greater than a width of the gap region, and wherein the first trench vertically overlaps with at least a portion of a top surface of the first chip structure or a portion of a top surface of the second chip structure.

公开(公告)号：US20210050326A1

公开(公告)日：2021-02-18

申请号：US16840772

申请日：2020-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun Seok CHOI

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip, a second semiconductor chip on a first surface of the first semiconductor chip, and a plurality of conductive pillars on the first surface of the first semiconductor chip and adjacent to at least one side of the second semiconductor chip. The first semiconductor chip includes a first circuit layer adjacent to the first surface of the first semiconductor chip. The second semiconductor chip and the plurality of conductive pillars are connected to the first surface of the first semiconductor chip.

公开(公告)号：US20250001433A1

公开(公告)日：2025-01-02

申请号：US18428946

申请日：2024-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk Min CHOI ,  Yun Seok CHOI ,  Byoung Chaul SON ,  Dong Cheol SIM ,  Jae Sun KIM ,  Jae Hyun SUNG ,  Eun Seok LEE

IPC: B03C1/30 ,  B24B37/34

Abstract: A substrate treating apparatus in which foreign substances are reduced by using a foreign substance collecting unit includes a magnetic structure. The substrate treating apparatus includes a roller configured to be disposed on a rail extending in a first direction and attached to a side surface of a carrier unit to move along the rail, and a foreign substance collecting unit installed on the side surface of the carrier unit, moving together with the roller, and configured to be spaced apart from the rail when the roller is disposed on the rail, wherein the foreign substance collecting unit includes a magnetic structure for adsorbing foreign magnetic substances using a magnetic force, and a case surrounding the magnetic structure.

公开(公告)号：US20140038353A1

公开(公告)日：2014-02-06

申请号：US13955259

申请日：2013-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji Hwang KIM ,  Tae Hong MIN ,  Chajea JO ,  Taeje CHO ,  Young Kun JEE ,  Yun Seok CHOI

IPC: H01L21/50

CPC classification number: H01L21/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/13 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/9202 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor package includes preparing a parent substrate including package board parts laterally spaced apart from each other, mounting a first chip including a through-via electrode on each of the package board parts, forming a first mold layer on the parent substrate having the first chips, planarizing the first mold layer to expose back sides of the first chips, etching the exposed back sides of the first chips to expose back sides of the through-via electrodes, forming a passivation layer on the planarized first mold layer, the etched back sides of the first chips, and the back sides of the through-via electrodes, and selectively removing the passivation layer to expose the back sides of the through-via electrodes.

Abstract translation: 制造半导体封装的方法包括：准备包括彼此横向隔开的封装板部分的母基板，在每个封装板部件上安装包括通孔电极的第一芯片，在母基板上形成第一模层 具有第一芯片，平坦化第一模具层以暴露第一芯片的背面，蚀刻第一芯片的暴露的背面以暴露通孔电极的背面，在平坦化的第一模具层上形成钝化层， 第一芯片的蚀刻背面和通孔电极的背面，并且选择性地去除钝化层以暴露通孔电极的背面。

公开(公告)号：US20240113003A1

公开(公告)日：2024-04-04

申请号：US18538458

申请日：2023-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yun Seok CHOI

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49894 ,  H01L25/0655 ,  H01L25/18 ,  H01L23/3675

Abstract: A semiconductor package includes an upper substrate having a first surface and a second surface which are opposite to each other, a semiconductor chip on the first surface of the upper substrate, a buffer layer on the second surface of the upper substrate, a mold layer between the second surface of the upper substrate and the buffer layer, a plurality of through-electrodes penetrating the upper substrate and the mold layer, an interconnection layer between the first surface of the upper substrate and the semiconductor chip and configured to electrically connect the semiconductor chip to the plurality of through-electrodes, and a plurality of bumps disposed on the buffer layer, spaced apart from the mold layer, and electrically connected to the plurality of through-electrodes. The mold layer includes an insulating material of which a coefficient of thermal expansion is greater than that of the upper substrate.

公开(公告)号：US20240046692A1

公开(公告)日：2024-02-08

申请号：US18131133

申请日：2023-04-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gwangjin LEE ,  Jaehyun LIM ,  Heeyoub KANG ,  Hyunjong MOON ,  Yun Seok CHOI ,  Inho CHOI

IPC: G06V40/13 ,  G06K19/073

CPC classification number: G06V40/1306 ,  G06K19/07354

Abstract: A fingerprint sensor package includes a first substrate having a core insulating layer with a first surface and a second surface, and a through-hole passing through the first surface and the second surface, a first bonding pad disposed on the second surface of the core insulating layer, and an external connection pad, a second substrate disposed in the through-hole of the core insulating layer and including a plurality of first sensing patterns, a plurality of second sensing patterns, and a second bonding pad, a conductive wire connecting the first bonding pad and the second bonding pad to each other, a controller chip disposed on the second substrate, and a molding layer disposed on the second surface of the core insulating layer, filling the through-hole, covering the second substrate and the first bonding pad, and spaced apart from the external connection pad.

公开(公告)号：US20220086373A1

公开(公告)日：2022-03-17

申请号：US17404198

申请日：2021-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Pan LIM ,  Irina KIM ,  Young Il SEO ,  Jeong Guk LEE ,  Yun Seok CHOI ,  Eun Doo HEO

IPC: H04N5/359 ,  G06N3/04 ,  H04N5/21 ,  H04N5/235 ,  H04N5/225

Abstract: An image processing device including a memory; and at least one image signal processor configured to: generate, using a first neural network, a feature value indicating whether to correct a global pixel value sensed during a unit frame interval, and generate a feature signal including the feature value; generate an image signal by merging the global pixel value with the feature signal; split a pixel value included in the image signal into a first sub-pixel value and a second sub-pixel value, split a frame feature signal included in the image signal into a first sub-feature value corresponding to the first sub-pixel value and a second sub-feature value corresponding to the second sub-pixel value, and generate a first sub-image signal including the first sub-pixel value and the first sub-feature value, and a second sub-image signal including the second sub-pixel value and the second sub-feature value; and sequentially correct the first sub-image signal and the second sub-image signal using a second neural network

公开(公告)号：US20170186602A1

公开(公告)日：2017-06-29

申请号：US15285570

申请日：2016-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Yun YANG ,  Seung Hyun LEE ,  Kyoung Sil PARK ,  Yool KANG ,  Yi Seul KIM ,  Yun Seok CHOI

IPC: H01L21/027 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L21/0271 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/02115 ,  H01L21/02282 ,  H01L21/02359 ,  H01L21/3081 ,  H01L51/0048

Abstract: A manufacturing method of a semiconductor device includes forming a hard mask layer on a semiconductor substrate using a hard mask composition. Hard mask patterns are formed by patterning the hard mask layer. Semiconductor patterns are formed by etching the semiconductor substrate using the hard mask patterns. The hard mask composition includes a plurality of first carbon nanotubes (CNTs) having a first length, a plurality of second CNTs having a second length, which is at least 3 times the first length, and a dispersing agent in which the first CNTs and the second CNTs are dispersed. The total mass of the first CNTs is 1 to 2.5 times the total mass of the second CNTs.

公开(公告)号：US20230164292A1

公开(公告)日：2023-05-25

申请号：US18158501

申请日：2023-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Won Seok LEE ,  Seong Wook SONG ,  Yun Seok CHOI

IPC: H04N5/917 ,  H04N19/14 ,  H04N23/80

CPC classification number: H04N5/917 ,  H04N19/14 ,  H04N23/80

Abstract: The present disclosure provides an image encoder. The image encoder is configured to encode an original image and reduce compression loss. The image encoder comprises an image signal processor and a compressor. The image signal processor is configured to receive a first frame image and a second frame image and generates a compressed image of the second frame image using a boundary pixel image of the first frame image. The image signal processor may include memory configured to store first reference pixel data which is the first frame image. The compressor is configured to receive the first reference pixel data from the memory and generate a bitstream obtained by encoding the second frame image based on a difference value between the first reference pixel data and the second frame image. The image signal processor generates a compressed image of the second frame image using the bitstream generated by the compressor.