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公开(公告)号：US11626143B2
公开(公告)日：2023-04-11
申请号：US17481995
申请日：2021-09-22
发明人： Hyeran Kim , Junyeol Lee , Jung-Hoon Chun
摘要： An output driver includes a pre driver including pre driving circuits, each including first and second pre pumps, and a main driver including main driving circuits, each including first and second main pumps. Each of the first and second pre pumps includes a first driving capacitor, and each of the first and second main pumps includes a second driving capacitor. During a first half cycle of a clock signal, the first pre pump and the first main pump perform a precharge operation, and the second pre pump and the second main pump perform a first driving operation, and during a second half cycle of the clock signal, the first pre pump and the first main pump perform the first driving operation, and the second pre pump and the second main pump perform the precharge operation. Capacitances of the first and second driving capacitors are different.
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公开(公告)号：US11955159B2
公开(公告)日：2024-04-09
申请号：US17703049
申请日：2022-03-24
发明人： Sungyong Cho , Kiheung Kim , Hyeran Kim
IPC分类号： G11C11/406 , G11C11/408 , H01L25/065 , H03M13/00 , H03M13/11
CPC分类号： G11C11/40615 , G11C11/4085 , H03M13/1105 , H03M13/611 , H01L25/0657 , H01L2225/06541
摘要： A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit and a refresh control circuit. The row hammer management circuit counts the number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller to store the counted values in each of the plurality of memory cell rows as count data, determines a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed more than a predetermined reference number of times, based on the counted values, and performs an internal read-update-write operation. The refresh control circuit receives the hammer address and to perform a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.
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公开(公告)号：US20230185460A1
公开(公告)日：2023-06-15
申请号：US18076628
申请日：2022-12-07
发明人： Kiheung Kim , Taeyoung Oh , Hyeran Kim , Sungyong Cho , Kyungsoo Ha
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0653 , G06F3/0659 , G06F3/0673
摘要： A semiconductor memory device includes a memory cell array, a row hammer management circuit and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The row hammer management circuit counts the number of instances of access of each of the memory cell rows, such as in response to the receipt of an active command, to store the counted values in count cells of each of the memory cell rows as count data and, in response to a first command, initiates an internal read-update-write operation to read the count data, to update the read count data, and to write the updated count data in the count cells. The control logic circuit may performs an internal write operation to write the updated count data in the count cells during a second write time interval that is smaller than a first write time interval associated with a normal write operation.
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公开(公告)号：US20240146335A1
公开(公告)日：2024-05-02
申请号：US18336285
申请日：2023-06-16
发明人： Sungrae Kim , Gilyoung Kang , Yujung Song , Hyeran Kim , Chisung Oh
CPC分类号： H03M13/2909 , G06F3/0611 , G06F3/0659 , G06F3/0673 , G06F11/10
摘要： A semiconductor memory device includes a memory cell array and an on-die error correction code (ECC) engine. The on-die ECC engine, during a write operation, generates a second main data by encoding a first main data with a random binary code, performs an ECC encoding on the second main data to generate a parity data and stores the second main data and the parity data in a target page in the memory cell array. The on-die ECC engine, during a read operation, reads the second main data and the parity data from the target page, performs an ECC decoding on the second main data based on the parity data to generate a syndrome in parallel with generating the first main data by encoding the second main data with the random binary code and corrects at least one error bit in the first main data based on the syndrome.
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公开(公告)号：US11947810B2
公开(公告)日：2024-04-02
申请号：US17743137
申请日：2022-05-12
发明人： Sungrae Kim , Hyeran Kim , Myungkyu Lee , Chisung Oh , Kijun Lee , Sunghye Cho , Sanguhn Cha
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0655 , G06F3/0656 , G06F3/0679
摘要： A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.
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6.发明公开公开(公告)号：US20230376414A1
公开(公告)日：2023-11-23
申请号：US18318906
申请日：2023-05-17
发明人： Sungrae Kim , Sungyong Cho , Minho Maeing , Gilyoung Kang , Hyeran Kim , Chisung Oh
IPC分类号： G06F12/06
CPC分类号： G06F12/06
摘要： A memory system includes a host system having a memory controller therein, which is configured to generate a command address signal. The memory controller includes a first bit signal generator configured to generate a data signal as a plurality of data bits, a second bit signal generator configured to generate a command address bus inversion bit (CABIB) having a high or low logic level that is a function of a number of data bits within the data signal having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the data signal and the CABIB having a high logic level is an even number. A storage system is also provided, which is configured to write or read data in response to the command address signal received from the host system. The memory controller is configured to set the CABIB to a high logic level when: (i) “n”, which is a number of bits included in the command address signal, is a positive integer greater than one, and (ii) a number of data bits within the data signal having a low logic level is greater than or equal to (n/2)−1.
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7.发明授权公开(公告)号：US11888476B2
公开(公告)日：2024-01-30
申请号：US17591093
申请日：2022-02-02
发明人： Daehyun Kwon , Hyejung Kwon , Hyeran Kim , Chisung Oh
IPC分类号： H03K19/017 , H03K19/00 , H03K19/17736 , H03K19/17772
CPC分类号： H03K19/01742 , H03K19/0005 , H03K19/1774 , H03K19/17772
摘要： An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.
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公开(公告)号：US20240029808A1
公开(公告)日：2024-01-25
申请号：US18174186
申请日：2023-02-24
发明人： Yujung Song , Sungrae Kim , Gilyoung Kang , Hyeran Kim , Chisung Oh
CPC分类号： G11C29/42 , G11C29/46 , G11C29/1201
摘要： A semiconductor memory device includes a memory cell array, an on-die error correction code (ECC) engine and a control logic circuit. The on-die ECC engine includes a first latch and a second latch. The control logic circuit sets the semiconductor memory device to a test mode in response to a first mode register set command. The on-die ECC engine, in the test mode, cuts off a connection with the memory cell array, receives a test data, stores the test data in the first latch, performs an ECC decoding on the test data stored in the first latch and a test parity data, stored in the second latch in response to a read command and provides an external device with a severity signal indicating whether the test data and the test parity data includes at least one error bit and the at least one error bit is correctable.
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9.发明公开公开(公告)号：US20230377669A1
公开(公告)日：2023-11-23
申请号：US18134776
申请日：2023-04-14
发明人： Wonyoung Choi , Gilyoung Kang , Sungrae Kim , Hyeran Kim , Jeongseok Park , Changkyu Seol
摘要： A memory device, an operating method of the memory device, and a test system including the memory device. The memory device may include a decoder group configured to receive a plurality of codewords including a plurality of symbols from outside of the memory device and to decode the plurality of codewords into data patterns, a memory cell array configured to store the data patterns received from the decoder group and including a plurality of memory cells, and an encoder configured to encode the data patterns into the plurality of codewords including the plurality of symbols. The plurality of codewords may include illegal codewords and normal codewords, and the decoder group may be further configured to convert the illegal codewords among the plurality of codewords into fixed patterns, and the encoder may be configured to output the plurality of codewords to the outside of the memory device.
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