公开(公告)号：US20140339547A1

公开(公告)日：2014-11-20

申请号：US14278705

申请日：2014-05-15

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Suguru HONDO ,  Daigo Ito

IPC: H01L29/786 ,  H01L23/31 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L23/3192 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78609 ,  H01L29/78648 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor with stable electric characteristics is provided. A transistor with small variation in electrical characteristics is provided. A miniaturized transistor is provided. A transistor having low off-state current is provided. A transistor having high on-state current is provided. A semiconductor device including the transistor is provided. One embodiment of the present invention is a semiconductor device including an island-shaped stack including a base insulating film and an oxide semiconductor film over the base insulating film; a protective insulating film facing a side surface of the stack and not facing a top surface of the stack; a first conductive film and a second conductive film which are provided over and in contact with the stack to be apart from each other; an insulating film over the stack, the first conductive film, and the second conductive film; and a third conductive film over the insulating film.

Abstract translation: 提供具有稳定电特性的晶体管。 提供了一种电特性变化小的晶体管。 提供了一种小型化的晶体管。 提供具有低截止电流的晶体管。 提供具有高导通电流的晶体管。 提供包括晶体管的半导体器件。 本发明的一个实施例是一种半导体器件，其包括在基底绝缘膜上的包括基底绝缘膜和氧化物半导体膜的岛状叠层; 面向堆叠的侧表面并且不面向堆叠的顶表面的保护性绝缘膜; 第一导电膜和第二导电膜，其设置在堆叠之间并与堆叠接触以彼此分开; 叠层上的绝缘膜，第一导电膜和第二导电膜; 和绝缘膜上的第三导电膜。

公开(公告)号：US20140326992A1

公开(公告)日：2014-11-06

申请号：US14258528

申请日：2014-04-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Suguru HONDO ,  Kazuya HANAOKA ,  Shinya SASAGAWA ,  Naoto KUSUMOTO

IPC: H01L29/786

CPC classification number: H01L29/78696 ,  H01L29/41733 ,  H01L29/7869

Abstract: Provided is a semiconductor device that can be miniaturized in a simple process and that can prevent deterioration of electrical characteristics due to miniaturization. The semiconductor device includes an oxide semiconductor layer, a first conductor in contact with the oxide semiconductor layer, and an insulator in contact with the first conductor. Further, an opening portion is provided in the oxide semiconductor layer, the first conductor, and the insulator. In the opening portion, side surfaces of the oxide semiconductor layer, the first conductor, and the insulator are aligned, and the oxide semiconductor layer and the first conductor are electrically connected to a second conductor by side contact.

Abstract translation: 提供了可以在简单的工艺中小型化并且可以防止由于小型化导致的电特性劣化的半导体器件。 半导体器件包括氧化物半导体层，与氧化物半导体层接触的第一导体和与第一导体接触的绝缘体。 此外，在氧化物半导体层，第一导体和绝缘体中设置有开口部。 在开口部分中，氧化物半导体层，第一导体和绝缘体的侧表面被对准，并且氧化物半导体层和第一导体通过侧面接触电连接到第二导体。

公开(公告)号：US20170162687A1

公开(公告)日：2017-06-08

申请号：US15432961

申请日：2017-02-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu MIYAIRI ,  Kazuya HANAOKA ,  Suguru HONDO ,  Shunpei YAMAZAKI

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/66969 ,  H01L29/7854 ,  H01L29/78621 ,  H01L29/7869 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A semiconductor device that operates at high speed. A semiconductor device with favorable switching characteristics. A highly integrated semiconductor device. A miniaturized semiconductor device. The semiconductor device is formed by: fainting a semiconductor film including an opening, on an insulating surface; forming a conductive film over the semiconductor film and in the opening, and removing the conductive film over the semiconductor film to form a conductive pillar in the opening; forming an island-shaped mask over the conductive pillar and the semiconductor film; etching the conductive pillar and the semiconductor film using the mask to form a first electrode and a first semiconductor; forming a gate insulating film on a top surface and a side surface of the first semiconductor; and forming a gate electrode that is in contact with a top surface of the gate insulating film and faces the top surface and the side surface of the first semiconductor.

公开(公告)号：US20150325708A1

公开(公告)日：2015-11-12

申请号：US14704101

申请日：2015-05-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuto YAKUBO ,  Suguru HONDO ,  Akihisa SHIMOMURA ,  Shunpei YAMAZAKI ,  Shuhei NAGATSUKA

IPC: H01L29/786 ,  H01L29/36 ,  H01L29/423 ,  H01L27/06 ,  H01L27/092 ,  H01L29/04 ,  H01L29/10

CPC classification number: H01L27/0688 ,  H01L21/8258 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/423 ,  H01L29/4238 ,  H01L29/7869 ,  H01L29/78696

Abstract: A transistor capable of being driven at high operating frequency is provided. The transistor includes first to third oxide semiconductor layers, a gate insulating layer, a gate electrode layer, and a portion in which the first to third oxide semiconductor layers are sequentially stacked. Channel length is less than 100 nm, and cutoff frequency at a source-drain voltage of higher than or equal to 1 V and lower than or equal to 2 V is higher than 1 GHz. The gate insulating layer is in contact with a top surface of the third oxide semiconductor layer. The gate electrode layer partly overlaps with the portion with the gate insulating layer positioned therebetween. The second oxide semiconductor layer includes a plurality of c-axis aligned crystal parts and a region in which the concentration of hydrogen measured by secondary ion mass spectrometry is lower than 2×1020 atoms/cm3.

Abstract translation: 提供能够以高工作频率驱动的晶体管。 晶体管包括第一至第三氧化物半导体层，栅极绝缘层，栅极电极层以及其中第一至第三氧化物半导体层顺序堆叠的部分。 通道长度小于100nm，源极 - 漏极电压高于或等于1V且低于或等于2V的截止频率高于1GHz。 栅极绝缘层与第三氧化物半导体层的顶表面接触。 栅极电极层与位于其间的栅极绝缘层的部分重叠。 第二氧化物半导体层包括多个c轴取向晶体部分和通过二次离子质谱法测量的氢浓度低于2×1020原子/ cm3的区域。

公开(公告)号：US20150263007A1

公开(公告)日：2015-09-17

申请号：US14645566

申请日：2015-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Yutaka OKAZAKI ,  Suguru HONDO

IPC: H01L27/105 ,  H01L29/04 ,  H01L29/24 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/045 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device with a transistor having favorable electrical characteristics is provided. The semiconductor device has a memory circuit and a circuit that are over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. A gate of the first transistor is electrically connected to the capacitor and one of a source and a drain of the second transistor. The circuit includes a third transistor and a fourth transistor that are electrically connected to each other in series. The first transistor and the third transistor each include an active layer including silicon, and the second transistor and the fourth transistor each include an active layer including an oxide semiconductor.

Abstract translation: 提供一种具有良好电特性的晶体管的半导体器件。 半导体器件具有位于相同衬底上的存储器电路和电路。 存储电路包括电容器，第一晶体管和第二晶体管。 第一晶体管的栅极电连接到电容器和第二晶体管的源极和漏极之一。 电路包括串联电连接的第三晶体管和第四晶体管。 第一晶体管和第三晶体管各自包括含有硅的有源层，第二晶体管和第四晶体管各自包括包含氧化物半导体的有源层。

公开(公告)号：US20160111546A1

公开(公告)日：2016-04-21

申请号：US14883732

申请日：2015-10-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Sachiaki TEZUKA ,  Tetsuhiro TANAKA ,  Toshihiko TAKEUCHI ,  Hideomi SUZAWA ,  Suguru HONDO

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7869 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78

Abstract: Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer. In the semiconductor device, the defect density in the oxide semiconductor layer is reduced.

Abstract translation: 为包括氧化物半导体的小型半导体器件提供稳定的电特性和高可靠性，并且制造半导体器件。 半导体器件包括基极绝缘层; 氧化物堆叠，其在所述基底绝缘层上方并且包括氧化物半导体层; 氧化层上的源电极层和漏电极层; 氧化层上的栅极绝缘层，源电极层和漏电极层; 栅绝缘层上的栅电极层; 以及在栅电极层上的层间绝缘层。 在半导体器件中，氧化物半导体层中的缺陷密度降低。

公开(公告)号：US20150221754A1

公开(公告)日：2015-08-06

申请号：US14688199

申请日：2015-04-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Suguru HONDO ,  Akihisa SHIMOMURA ,  Masaki KOYAMA ,  Motomu KURATA ,  Kazuya HANAOKA ,  Sho NAGAMATSU ,  Kosei NEI ,  Toru HASEGAWA

IPC: H01L29/66 ,  H01L21/46

CPC classification number: H01L29/66969 ,  H01L21/46 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696

Abstract: A transistor including an oxide semiconductor film, which has stable electric characteristics is provided. A transistor including an oxide semiconductor film, which has excellent on-state characteristics is also provided. A semiconductor device in which an oxide semiconductor film having low resistance is formed and the resistance of a channel region of the oxide semiconductor film is increased. Note that an oxide semiconductor film is subjected to a process for reducing the resistance to have low resistance. The process for reducing the resistance of the oxide semiconductor film may be a laser process or heat treatment at a temperature higher than or equal to 450° C. and lower than or equal to 740° C., for example. A process for increasing the resistance of the channel region of the oxide semiconductor film having low resistance may be performed by plasma oxidation or implantation of oxygen ions, for example.

Abstract translation: 提供具有稳定电特性的包括氧化物半导体膜的晶体管。 还提供了具有优异的导通状态特性的包括氧化物半导体膜的晶体管。 其中形成具有低电阻的氧化物半导体膜并且氧化物半导体膜的沟道区的电阻增加的半导体器件。 注意，氧化物半导体膜经受用于降低电阻以降低电阻的工艺。 用于降低氧化物半导体膜的电阻的方法可以是例如在高于或等于450℃且低于或等于740℃的温度下的激光处理或热处理。 例如，可以通过等离子体氧化或氧离子的注入来提高具有低电阻的氧化物半导体膜的沟道区域的电阻的方法。

公开(公告)号：US20130207101A1

公开(公告)日：2013-08-15

申请号：US13758291

申请日：2013-02-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Yuki HATA ,  Suguru HONDO

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/78696

Abstract: A transistor including an oxide semiconductor and having favorable operation characteristics is provided. Further, by using the transistor, a semiconductor having improved operation characteristics can be provided. In planar view, one of a source electrode and a drain electrode of the transistor is surrounded by a ring-shaped gate electrode. Further, in planar view, one of the source electrode and the drain electrode of the transistor is surrounded by a channel formation region. Accordingly, the source electrode is not electrically connected to the drain electrode through a parasitic channel generated in an end portion of an island-shaped oxide semiconductor layer.

公开(公告)号：US20150318402A1

公开(公告)日：2015-11-05

申请号：US14799015

申请日：2015-07-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Atsuo ISOBE ,  Yuki HATA ,  Suguru HONDO

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L49/02 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L27/1255 ,  H01L28/60 ,  H01L29/0692 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/78696

Abstract: A transistor including an oxide semiconductor and having favorable operation characteristics is provided. Further, by using the transistor, a semiconductor having improved operation characteristics can be provided. In planar view, one of a source electrode and a drain electrode of the transistor is surrounded by a ring-shaped gate electrode. Further, in planar view, one of the source electrode and the drain electrode of the transistor is surrounded by a channel formation region. Accordingly, the source electrode is not electrically connected to the drain electrode through a parasitic channel generated in an end portion of an island-shaped oxide semiconductor layer.

Abstract translation: 提供一种包含氧化物半导体并具有良好操作特性的晶体管。 此外，通过使用晶体管，可以提供具有改善的操作特性的半导体。 在平面图中，晶体管的源极和漏极中的一个被环形栅电极包围。 此外，在平面图中，晶体管的源电极和漏电极之一被沟道形成区域包围。 因此，源电极通过在岛状氧化物半导体层的端部中产生的寄生沟道而不与漏电极电连接。

公开(公告)号：US20150255310A1

公开(公告)日：2015-09-10

申请号：US14635324

申请日：2015-03-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Suguru HONDO ,  Naoto YAMADE

IPC: H01L21/425 ,  H01L21/385 ,  H01L21/477 ,  H01L21/465

CPC classification number: H01L21/425 ,  H01L21/465 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: Provided is a method for manufacturing a semiconductor device with favorable electrical characteristics. The following steps are performed in the following order: forming an oxide semiconductor film over a substrate having a substantially planar surface; selectively etching the oxide semiconductor film to form an oxide semiconductor layer; implanting an oxygen ion on a top surface of the oxide semiconductor layer and a side surface of the oxide semiconductor layer in a cross-section perpendicular to the substantially planar surface in a channel width direction of the oxide semiconductor layer from an angle 0°

Abstract translation: 提供一种具有良好的电气特性的半导体器件的制造方法。 按照以下顺序进行以下步骤：在具有大致平坦表面的基板上形成氧化物半导体膜; 选择性地蚀刻氧化物半导体膜以形成氧化物半导体层; 在氧化物半导体层的沟道宽度方向的垂直于基本上平坦的表面的截面中，角度为0°，将氧离子注入到氧化物半导体层的顶表面和氧化物半导体层的侧表面上 ; <90°; 在所述氧化物半导体层上形成绝缘层，并对所述氧化物半导体层进行热处理以将氧扩散到所述氧化物半导体层中。