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公开(公告)号：US09413236B2
公开(公告)日：2016-08-09
申请号：US14571605
申请日：2014-12-16
Inventor： Jin-Hyuk Kim , Dong-Hoon Jung , Kyung-Ho Ryu , Seong-Ook Jung , Byoung-Chan Oh
Abstract: A voltage converter includes a power supply circuit configured to generate an output voltage based on an input voltage in response to a control signal, and a power supply control circuit configured to generate the control signal based on a reference clock signal and the output voltage.
Abstract translation: 电压转换器包括：电源电路，被配置为响应于控制信号产生基于输入电压的输出电压;以及电源控制电路，被配置为基于参考时钟信号和输出电压产生控制信号。
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公开(公告)号：US09368180B2
公开(公告)日：2016-06-14
申请号：US14511089
申请日：2014-10-09
Applicant: SK hynix Inc.
Inventor： Byoung-Chan Oh , Dong-Keun Kim
CPC classification number: G11C11/1675 , G11C11/16 , G11C11/161 , G11C11/1693 , G11C11/1697 , G11C29/1201 , G11C29/48 , G11C29/84 , G11C2029/5006
Abstract: In an electronic device including a semiconductor memory, the semiconductor memory may include a unit storage cell including a variable resistor having a resistance value that is changed according to current flowing through both terminals of the variable resistor and a selection element that is electrically coupled to one terminal of the variable resistor, a unit current generation section that generates the current flowing through both terminals by using predetermined voltage according to a polarity of current data as compared with existing data, and a pad that receives the predetermined voltage from an exterior and allows the current flowing through both terminals to be measured from an exterior.
Abstract translation: 在包括半导体存储器的电子设备中，半导体存储器可以包括单元存储单元，该单元存储单元包括可变电阻器，该可变电阻器具有根据流过可变电阻器两端的电流而改变的电阻值，以及电耦合到一个的选择元件 可变电阻器的端子，通过使用与现有数据相比的当前数据的极性使用预定电压来生成流过两个端子的电流的单元电流产生部分，以及从外部接收预定电压的焊盘， 从外部流过要测量的两个端子的电流。
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公开(公告)号：US09450575B2
公开(公告)日：2016-09-20
申请号：US14624355
申请日：2015-02-17
Applicant: SK hynix Inc.
Inventor： Byoung-Chan Oh
CPC classification number: H03K5/2472 , G11C7/065 , G11C7/08 , G11C7/12 , G11C11/1673 , G11C13/004 , G11C2013/0054 , G11C2207/002 , G11C2207/063
Abstract: A current comparator may include a current comparison block configured to compare current flowing through first and second input terminals; a first current control unit configured to control current flowing through the first input terminal in response to a voltage of a first node; a second current control unit configured to control current flowing through the second input terminal in response to a voltage of a second node; a first driving unit configured to drive the first node with a first voltage higher than a read voltage in a non-comparison period, and drive the first node with the read voltage in a comparison period; and a second driving unit configured to drive the second node with a second voltage higher than a reference voltage in the non-comparison period, and drive the second node with the reference voltage in the comparison period.
Abstract translation: 电流比较器可以包括电流比较块，其被配置为比较流过第一和第二输入端的电流; 第一电流控制单元，被配置为响应于第一节点的电压来控制流过第一输入端子的电流; 第二电流控制单元，被配置为响应于第二节点的电压来控制流过所述第二输入端子的电流; 第一驱动单元，被配置为在非比较周期中以比读取电压高的第一电压驱动第一节点，并且在比较周期中以读取电压驱动第一节点; 以及第二驱动单元，被配置为在所述非比较周期中以比所述参考电压高的第二电压驱动所述第二节点，并且在所述比较周期中以所述参考电压驱动所述第二节点。
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公开(公告)号：US20160072493A1
公开(公告)日：2016-03-10
申请号：US14624355
申请日：2015-02-17
Applicant: SK hynix Inc.
Inventor： Byoung-Chan Oh
CPC classification number: H03K5/2472 , G11C7/065 , G11C7/08 , G11C7/12 , G11C11/1673 , G11C13/004 , G11C2013/0054 , G11C2207/002 , G11C2207/063
Abstract: A current comparator may include a current comparison block configured to compare current flowing through first and second input terminals; a first current control unit configured to control current flowing through the first input terminal in response to a voltage of a first node; a second current control unit configured to control current flowing through the second input terminal in response to a voltage of a second node; a first driving unit configured to drive the first node with a first voltage higher than a read voltage in a non-comparison period, and drive the first node with the read voltage in a comparison period; and a second driving unit configured to drive the second node with a second voltage higher than a reference voltage in the non-comparison period, and drive the second node with the reference voltage in the comparison period.
Abstract translation: 电流比较器可以包括电流比较块，其被配置为比较流过第一和第二输入端的电流; 第一电流控制单元，被配置为响应于第一节点的电压来控制流过第一输入端子的电流; 第二电流控制单元，被配置为响应于第二节点的电压来控制流过所述第二输入端子的电流; 第一驱动单元，被配置为在非比较周期中以比读取电压高的第一电压驱动第一节点，并且在比较周期中以读取电压驱动第一节点; 以及第二驱动单元，被配置为在所述非比较周期中以比所述参考电压高的第二电压驱动所述第二节点，并且在所述比较周期中以所述参考电压驱动所述第二节点。
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公开(公告)号：US09154140B1
公开(公告)日：2015-10-06
申请号：US14576083
申请日：2014-12-18
Inventor： Dong-Hoon Jung , Jin-Hyuk Kim , Kyung-Ho Ryu , Seong-Ook Jung , Byoung-Chan Oh
CPC classification number: H03L7/0812 , H03L7/0818 , H03L7/087 , H03L7/10
Abstract: A delay locked loop includes a variable delay line circuit configured to delay a pulse selection circuit output to generate an output signal, a delay model circuit to delay the output signal to generate a first feedback signal, a first phase comparator circuit to control the variable delay line circuit according to the input signal and the first feedback signal, a pulse generation circuit to generate a pulse signal according to the input signal and the first feedback signal, a pulse retainer circuit to delay the output signal to generate a second feedback signal, a pulse selection circuit to select the pulse signal generated by the pulse generation circuit or the second feedback signal as the pulse selection circuit output during the tracking operation, and a second phase comparator circuit to control the variable delay line circuit according to the pulse selection circuit output and the output signal.
Abstract translation: 延迟锁定环包括可变延迟线电路，其被配置为延迟脉冲选择电路输出以产生输出信号;延迟模型电路，用于延迟输出信号以产生第一反馈信号;第一相位比较器电路，用于控制可变延迟 根据输入信号和第一反馈信号的线路电路，产生根据输入信号和第一反馈信号的脉冲信号的脉冲发生电路，延迟输出信号以产生第二反馈信号的脉冲保持器电路， 脉冲选择电路，用于选择由脉冲发生电路产生的脉冲信号或第二反馈信号作为跟踪操作期间输出的脉冲选择电路;以及第二相位比较器电路，用于根据脉冲选择电路输出控制可变延迟线电路 和输出信号。
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Patent Agency Ranking
公开(公告)号：US20140337568A1
公开(公告)日：2014-11-13
申请号：US14219281
申请日：2014-03-19
Applicant: SK HYNIX INC.
Inventor： Byoung-Chan Oh , Yoon-Jae Shin
CPC classification number: G06F3/0673 , G05F1/465 , G05F1/466 , G05F1/575 , G05F1/70 , G05F3/30 , G11C5/147 , G11C11/1697 , G11C13/0038 , H02M3/1563
Abstract: Provided is an electronic device including a power supply circuit. The power supply circuit includes: a voltage driving unit configured to pull-up drive an output node and generate an output voltage; and a driving control unit configured to receive the output voltage, disable the voltage driving unit from the time at which a divided voltage obtained by dividing the output voltage at a set ratio becomes higher than a first level, and enable the voltage driving unit from the time at which the divided voltage becomes lower than a second level, which is higher than the first level.
Abstract translation: 提供了一种包括电源电路的电子设备。 电源电路包括：电压驱动单元，被配置为上拉驱动输出节点并产生输出电压; 以及驱动控制单元，被配置为接收所述输出电压，从所述电压驱动单元从通过将所述输出电压除以设定比率而获得的分压值变得高于第一电平的时间来禁用所述电压驱动单元，并且使得所述电压驱动单元从 分压电压变得低于高于第一电平的第二电平的时间。
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公开(公告)号：US09542124B2
公开(公告)日：2017-01-10
申请号：US14219281
申请日：2014-03-19
Applicant: SK hynix Inc.
Inventor： Byoung-Chan Oh , Yoon-Jae Shin
IPC: G06F1/26 , G05F1/46 , G06F3/06 , G11C5/14 , H02M3/156 , G11C11/16 , G11C13/00 , G05F3/30 , G05F1/70 , G05F1/575
CPC classification number: G06F3/0673 , G05F1/465 , G05F1/466 , G05F1/575 , G05F1/70 , G05F3/30 , G11C5/147 , G11C11/1697 , G11C13/0038 , H02M3/1563
Abstract: Provided is an electronic device including a power supply circuit. The power supply circuit includes: a voltage driving unit configured to pull-up drive an output node and generate an output voltage; and a driving control unit configured to receive the output voltage, disable the voltage driving unit from the time at which a divided voltage obtained by dividing the output voltage at a set ratio becomes higher than a first level, and enable the voltage driving unit from the time at which the divided voltage becomes lower than a second level, which is higher than the first level.
Abstract translation: 提供了一种包括电源电路的电子设备。 电源电路包括：电压驱动单元，被配置为上拉驱动输出节点并产生输出电压; 以及驱动控制单元，被配置为接收所述输出电压，从所述电压驱动单元从通过将所述输出电压除以设定比率而获得的分压值变得高于第一电平的时间来禁用所述电压驱动单元，并且使得所述电压驱动单元从 分压电压变得低于高于第一电平的第二电平的时间。
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公开(公告)号：US20140241039A1
公开(公告)日：2014-08-28
申请号：US14191300
申请日：2014-02-26
Applicant: SK hynix Inc.
Inventor： Byoung-Chan Oh
IPC: G11C13/00
CPC classification number: G11C11/5607 , G11C8/08 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C16/08 , G11C2211/5643 , G11C2211/5645
Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a plurality of variable resistance elements; a plurality of read voltage application terminals configured to supply different levels of read voltages to respective one ends of the plurality of variable resistance elements; and an analog-to-digital conversion unit configured to generate multi-bit digital data corresponding to a total current which is acquired by summing currents flowing through the plurality of variable resistance elements.
Abstract translation: 一种包括半导体存储器的电子设备。 半导体存储器包括多个可变电阻元件; 多个读取电压施加端子，被配置为向所述多个可变电阻元件的相应一端提供不同电平的读取电压; 以及模拟 - 数字转换单元，被配置为生成对应于通过对流过所述多个可变电阻元件的电流求和而获得的总电流的多位数字数据。
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公开(公告)号：US09437289B2
公开(公告)日：2016-09-06
申请号：US14219381
申请日：2014-03-19
Applicant: SK hynix Inc.
Inventor： Byoung-Chan Oh , Yoon-Jae Shin
CPC classification number: G11C13/003 , G11C7/04 , G11C11/16 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1697 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2213/74 , G11C2213/78 , G11C2213/79
Abstract: Provided an electronic device including a semiconductor memory unit. The semiconductor memory unit includes: a plurality of storage cells each including a variable resistance element of which resistance is changed in response to a current flowing across the variable resistance element and a selecting element coupled to one end of the variable resistance element; a plurality of word lines corresponding to the respective storage cells and each coupled to a selecting element of a corresponding storage cell; a first line coupled to one ends of the plurality of storage cells; a second line coupled to the other ends of the plurality of storage cells; a voltage adjuster configured to adjust the voltage levels of back bias voltages of the selecting elements of the plurality of storage cells; and an access control unit electrically coupled to the first and second lines and passing an access current to a selected storage cell among the plurality of storage cells.
Abstract translation: 提供一种包括半导体存储单元的电子设备。 半导体存储单元包括：多个存储单元，每个存储单元包括响应于流过可变电阻元件的电流而改变电阻的可变电阻元件和耦合到可变电阻元件的一端的选择元件; 对应于各个存储单元的多个字线，并且每个字线耦合到对应的存储单元的选择元件; 耦合到所述多个存储单元的一端的第一线; 耦合到所述多个存储单元的另一端的第二线; 电压调节器，被配置为调整所述多个存储单元的选择元件的反向偏置电压的电压电平; 以及访问控制单元，其电耦合到所述第一和第二线路，并且将访问电流传递到所述多个存储单元中的所选择的存储单元。
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公开(公告)号：US09384828B2
公开(公告)日：2016-07-05
申请号：US14191300
申请日：2014-02-26
Applicant: SK hynix Inc.
Inventor： Byoung-Chan Oh
CPC classification number: G11C11/5607 , G11C8/08 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C16/08 , G11C2211/5643 , G11C2211/5645
Abstract: An electronic device including a semiconductor memory. The semiconductor memory includes a plurality of variable resistance elements; a plurality of read voltage application terminals configured to supply different levels of read voltages to respective one ends of the plurality of variable resistance elements; and an analog-to-digital conversion unit configured to generate multi-bit digital data corresponding to a total current which is acquired by summing currents flowing through the plurality of variable resistance elements.
Abstract translation: 一种包括半导体存储器的电子设备。 半导体存储器包括多个可变电阻元件; 多个读取电压施加端子，被配置为向多个可变电阻元件的相应一端提供不同电平的读取电压; 以及模拟 - 数字转换单元，被配置为生成对应于通过对流过所述多个可变电阻元件的电流求和来获得的总电流的多位数字数据。
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