公开(公告)号：US11075172B2

公开(公告)日：2021-07-27

申请号：US16389849

申请日：2019-04-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Santo Alessandro Smerzi ,  Michele Calabretta ,  Alessandro Sitta ,  Crocifisso Marco Antonio Renna ,  Giuseppe D'Arrigo

IPC: H01L23/00 ,  H01L21/52 ,  H01L23/14 ,  H01L23/06 ,  H01L29/78

Abstract: A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature. Furthermore, additional stress can be enhanced by means of different embodiments involving the support, such as ring or multi-layer frame.

公开(公告)号：US11894432B2

公开(公告)日：2024-02-06

申请号：US17573449

申请日：2022-01-11

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Crocifisso Marco Antonio Renna ,  Antonio Landi ,  Brunella Cafra

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/41708 ,  H01L29/401 ,  H01L29/456 ,  H01L29/66333 ,  H01L29/7395

Abstract: Various embodiments provide a vertical-conduction semiconductor device that includes: a silicon substrate having a front face and a rear face; a front-side structure arranged on the front face of the substrate, having at least one current-conduction region at the front face; and a back side metal structure, arranged on the rear face of the substrate, in electrical contact with the substrate and constituted by a stack of metal layers. The back side metal structure is formed by: a first metal layer; a silicide region, interposed between the rear face of the substrate and the first metal layer and in electrical contact with the aforesaid rear face; and a second metal layer arranged on the first metal layer.

公开(公告)号：US11756916B2

公开(公告)日：2023-09-12

申请号：US17933016

申请日：2022-09-16

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Michele Calabretta ,  Crocifisso Marco Antonio Renna ,  Sebastiano Russo ,  Marco Alfio Torrisi

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/00 ,  H01L23/31 ,  H01L23/495 ,  B23K101/40

CPC classification number: H01L24/29 ,  B23K35/262 ,  C22C13/00 ,  H01L23/3121 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49579 ,  H01L24/27 ,  H01L24/32 ,  H01L24/83 ,  B23K2101/40 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/2912 ,  H01L2224/29105 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29139 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48245 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83801 ,  H01L2924/014 ,  H01L2924/20109

Abstract: A method for soldering a die obtained using the semiconductor technique with a leadframe, comprising the steps of providing a leadframe, which has at least one surface made at least partially of copper; providing a die, which has at least one surface coated with a metal layer; applying to the surface a solder alloy comprising at least 40 wt % of tin or at least 50% of indium or at least 50% of gallium, without lead, and heating the alloy to a temperature of at least 380° C. to form a drop of solder alloy; providing a die, which has at least one surface coated with a metal layer; and setting the metal layer in contact with the drop of solder alloy to form the soldered connection with the leadframe. Moreover, a device obtained with said method is provided.

公开(公告)号：US09777317B2

公开(公告)日：2017-10-03

申请号：US13956677

申请日：2013-08-01

Applicant: STMicroelectronics S.r.l. ,  bioMérieux S.A.

Inventor： Giuseppe Emanuele Spoto ,  Luigi Giuseppe Occhipinti ,  Cristian Dall'Oglio ,  Crocifisso Marco Antonio Renna ,  Laurent Drazek

IPC: C12Q1/68 ,  B01L3/00

CPC classification number: C12Q1/686 ,  B01L3/5027 ,  B01L2300/0816 ,  B01L2300/0864

Abstract: A microfluidic device (1000-1005), comprising: a semiconductor body (2) having a first side (2a) and a second side (2b) opposite to one another, and housing, at the first side, a plurality of wells (4), having a first depth; an inlet region (30) forming an entrance point for a fluid to be supplied to the wells; a main channel (6a) fluidically connected to the inlet region, and having a second depth; and a plurality of secondary channels (6b) fluidically connecting the main channel to a respective well, and having a third depth. The first depth is higher than the second depth, which in turn is higher than the third depth. According to an aspect, the microfluidic device further comprises a cover layer (8), arranged above the first side of the semiconductor body, configured for sealing the wells and provided with at least a first valve hole (54) which extends through the cover layer and overlaps, at least partially, the secondary channels; and a flexible layer (14), arranged above the cover layer and provided with at least a protrusion (74) extending through the first valve hole towards the semiconductor body and overlapping, at least partially, the secondary channels, the flexible layer being configured such that, when a pressure is applied on it, the protrusion contacts the semiconductor body and enters the secondary channels thus fluidically isolating the wells from one another.

公开(公告)号：US09190539B2

公开(公告)日：2015-11-17

申请号：US14600537

申请日：2015-01-20

Applicant: STMICROELECTRONICS, S.R.L.

Inventor： Crocifisso Marco Antonio Renna

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L31/02 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L31/02019 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/0401 ,  H01L2224/05 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/14 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: An embodiment of a die comprising: a semiconductor body including a front side, a back side, and a lateral surface; an electronic device, formed in said semiconductor body and including an active area facing the front side; a vertical conductive connection, extending through the semiconductor body and defining a conductive path between the front side and the back side of the semiconductor body; and a conductive contact, defining a conductive path on the front side of the semiconductor body, between the active area and the vertical conductive connection, wherein the vertical conductive connection is formed on the lateral surface of the die, outside the active area.

公开(公告)号：US11837558B2

公开(公告)日：2023-12-05

申请号：US17372115

申请日：2021-07-09

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Santo Alessandro Smerzi ,  Michele Calabretta ,  Alessandro Sitta ,  Crocifisso Marco Antonio Renna ,  Giuseppe D'Arrigo

IPC: H01L23/06 ,  H01L23/00 ,  H01L21/52 ,  H01L23/14 ,  H01L29/78

CPC classification number: H01L23/564 ,  H01L21/52 ,  H01L23/06 ,  H01L23/14 ,  H01L29/7842

Abstract: A process for manufacturing a strained semiconductor device envisages: providing a die of semiconductor material, in which elementary components of the semiconductor device have been integrated by means of initial front-end steps; and coupling, using the die-attach technique, the die to a support, at a coupling temperature. The aforesaid coupling step envisages selecting the value of the coupling temperature at a value higher than an operating temperature of use of the semiconductor device, and moreover selecting the material of the support so that it is different from the material of the die in order to determine, at the operating temperature, a coupling stress that is a function of the different values of the coefficients of thermal expansion of the materials of the die and of the support and of the temperature difference between the coupling temperature and the operating temperature. Furthermore, additional stress can be enhanced by means of different embodiments involving the support, such as ring or multi-layer frame.

公开(公告)号：US11482503B2

公开(公告)日：2022-10-25

申请号：US16811964

申请日：2020-03-06

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Michele Calabretta ,  Crocifisso Marco Antonio Renna ,  Sebastiano Russo ,  Marco Alfio Torrisi

IPC: H01L23/00 ,  B23K35/26 ,  C22C13/00 ,  H01L23/31 ,  H01L23/495 ,  B23K101/40

Abstract: A method for soldering a die obtained using the semiconductor technique with a leadframe, comprising the steps of providing a leadframe, which has at least one surface made at least partially of copper; providing a die, which has at least one surface coated with a metal layer; applying to the surface a solder alloy comprising at least 40 wt % of tin or at least 50% of indium or at least 50% of gallium, without lead, and heating the alloy to a temperature of at least 380° C. to form a drop of solder alloy; providing a die, which has at least one surface coated with a metal layer; and setting the metal layer in contact with the drop of solder alloy to form the soldered connection with the leadframe. Moreover, a device obtained with said method is provided.