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1.发明授权公开(公告)号：US10050661B2
公开(公告)日：2018-08-14
申请号：US15614667
申请日：2017-06-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jun-Ho Huh , Ho-Rang Jang , Seok-Chan Kim , In-Tae Kang , Sang-Heon Lee , Kwan-Yeob Chae , June-Hee Lee , Sang-Hune Park , Jae-Chol Lee , Hyung-Kweon Lee
Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
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公开(公告)号：US20140203335A1
公开(公告)日：2014-07-24
申请号：US14155579
申请日：2014-01-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-Yeol Song , June-Hee Lee , Hye-Lan Lee , Sang-Jin Hyun , Sang-Bom Kang
CPC classification number: H01L29/78 , H01L21/28088 , H01L21/823842 , H01L27/1104 , H01L29/51 , H01L29/6681
Abstract: A semiconductor device includes an insulating film on a substrate and including a trench, a gate insulating film in the trench, a DIT (Density of Interface Trap) improvement film on the gate insulating film to improve a DIT of the substrate, and a first conductivity type work function adjustment film on the DIT improvement film. Related methods of forming semiconductor devices are also disclosed.
Abstract translation: 半导体器件包括在衬底上的绝缘膜，其包括沟槽，沟槽中的栅极绝缘膜，栅极绝缘膜上的DIT（界面陷阱密度）改进膜，以改善衬底的DIT，以及第一导电性 DIT改进膜上的工作功能调整膜。 还公开了形成半导体器件的相关方法。
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公开(公告)号：US10536260B2
公开(公告)日：2020-01-14
申请号：US15468564
申请日：2017-03-24
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae Chol Lee , Bong Kyu Kim , June-Hee Lee
Abstract: A baseband IC for performing digital communication with an RFIC and a device including the same. The baseband IC for performing digital communication with an RFIC includes a digital interface circuit configured to receive a frame signal including at least one sampled signal from the RFIC according to a digital interface protocol, reconstruct the at least one sampled signal from the frame signal, and transfer the reconstructed sampled signal to a baseband modem in synchronization with a reception reference signal, and a sample synchronization manager configured to generate the reception reference signal, wherein the frame signal is transmitted from the RFIC to the baseband IC in synchronization with a transmission reference signal.
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4.发明授权公开(公告)号：US10516433B2
公开(公告)日：2019-12-24
申请号：US16037024
申请日：2018-07-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jun-Ho Huh , Ho-Rang Jang , Seok-Chan Kim , In-Tae Kang , Sang-Heon Lee , Kwan-Yeob Chae , June-Hee Lee , Sang-Hune Park , Jae-Chol Lee , Hyung-Kweon Lee
Abstract: A modem chip communicates with a radio frequency (RF) chip and includes a digital interface configured to receive data including a plurality of samples from the RF chip based on digital communication. A logic block generates a frame synchronization signal based on a clock signal in the modem chip, provides the generated frame synchronization signal to the digital interface, and receives the plurality of samples in synchronization with the frame synchronization signal.
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5.发明申请公开(公告)号：US20180331100A1
公开(公告)日：2018-11-15
申请号：US16028272
申请日：2018-07-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hye-Lan Lee , Sang-Bom Kang , Jae-Jung Kim , Moon-Kyu Park , Jae-Yeol Song , June-Hee Lee , Yong-Ho Ha , Sang-Jin Hyun
IPC: H01L27/088 , H01L21/84 , H01L29/66 , H01L29/49 , H01L21/8238 , H01L27/12 , H01L27/092 , H01L29/51 , H01L29/165
CPC classification number: H01L27/0886 , H01L21/823821 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/165 , H01L29/4966 , H01L29/517 , H01L29/66545
Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.
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Patent Agency Ranking
公开(公告)号：US09407479B2
公开(公告)日：2016-08-02
申请号：US14710713
申请日：2015-05-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： June-Hee Lee , Jun-Han Bae , Bong-Kyu Kim , Jong-Jae Ruy
CPC classification number: H04L25/4902 , H04L7/0331 , H04L25/0272
Abstract: A pulse width modulation (PWM) data recovery device includes a differential-to-single (DTS) circuit configured to generate a PWM bit using a differential data signal including a differential positive data signal and a differential negative data signal, and an alignment buffer configured to activate a bit lock signal by detecting a synch pattern, recover symbol data by receiving the PWM bit in synchronization with one of the differential positive data signal and the differential negative data signal, and transmit the symbol data in synchronization with a reference clock.
Abstract translation: 脉冲宽度调制（PWM）数据恢复装置包括差分到单（DTS）电路，其被配置为使用包括差分正数据信号和差分负数据信号的差分数据信号产生PWM位，以及配置 通过检测同步模式来激活位锁定信号，通过与差分正数据信号和差分负数据信号之一同步地接收PWM位来恢复符号数据，并且与参考时钟同步地发送符号数据。
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公开(公告)号：US10943524B2
公开(公告)日：2021-03-09
申请号：US16427856
申请日：2019-05-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-Chul Choi , Sung-Ho Kang , June-Hee Lee , Han-Kyul Lim , Byung-Wook Cho
Abstract: A device for generating restoration data by descrambling scramble data includes a linear feedback shift register configured to receive a first clock including a plurality of edges and sequentially generate a plurality of seeds including first to N−1th seeds (where N is a natural number of 2 or greater) respectively corresponding to first to N−1th edges among the plurality of edges, a seed calculator configured to calculate an Nth seed corresponding to an Nth edge among the plurality of edges by using the first seed, and a descrambler configured to descramble the scramble data by using the plurality of seeds generated by the linear feedback shift register and the Nth seed calculated by the seed calculator. The linear feedback shift register is further configured to generate an N+1th seed by using the Nth seed.
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公开(公告)号：US10673562B2
公开(公告)日：2020-06-02
申请号：US16257249
申请日：2019-01-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： June-Hee Lee , Donghyuk Lim
Abstract: A signal receiving circuit may include a receiving equalizer and a sequence estimator. The receiving equalizer may be configured to compensate an inter-symbol interference in a signal from an external to output an equalization data, based on a receiving signal from an outside. The sequence estimator may be configured to determine a termination symbol, based on the equalization data, to perform a decoding on the receiving signal, based on the determined termination symbol, and to output the decoded receiving signal as a sequence data.
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公开(公告)号：US10466301B1
公开(公告)日：2019-11-05
申请号：US16181241
申请日：2018-11-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： June-Hee Lee , Byungwook Cho , Bongkyu Kim
IPC: H04B17/00 , H04L25/03 , G01R31/317 , H04B1/16
Abstract: A receiver includes a sampler that samples first voltage levels corresponding to a first logical value of data and second voltage levels corresponding to a second logical value of the data, based on a sampling clock. An equalizer receives and adjusts the first and second voltage levels. A clock and data recovery circuit recovers the sampling clock, based on the first and second voltage levels from the equalizer. An eye opening measurement circuit: (1) tracks a first sigma level by a first step unit depending on upper voltage levels greater than a first reference voltage level among the first voltage levels, (2) tracks a second sigma level by a second step unit depending on lower voltage levels less than a second reference voltage level among the second voltage levels, and (3) calculates a difference between the first sigma level and the second sigma level.
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公开(公告)号：US09658643B2
公开(公告)日：2017-05-23
申请号：US14623069
申请日：2015-02-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Young-Kyun Jeong , Jung-Hoon Chun , June-Hee Lee , Won-Ho Choi
CPC classification number: G06F1/08 , G06F13/4068
Abstract: A data interface includes a first sampler sampling a first bitset and a second sampler sampling a second bitset. The first bitset includes a first bit which is included in a first image data and a third bit which is included in a second image, and the second bitset includes a second bit which is included in the first image data and is a higher-order bit than the first bit and a fourth bit which is included in the second image data and is a higher-order bit than the third bit. The data interface further includes a clock generator configured to adjust a sampling timing of the first and second bitsets based on a multi-phase clock, and a clock data recovery (CDR) circuit shared by the first sampler, the second sampler and configured to output the multi-phase clock to the clock generator.
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