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    3D semiconductor devices and methods of fabricating same
    2.
    发明授权
    3D semiconductor devices and methods of fabricating same 有权
    3D半导体器件及其制造方法

    公开(公告)号：US08564050B2

    公开(公告)日：2013-10-22

    申请号：US13297493

    申请日：2011-11-16

    申请人： Sang-Yong Park ,  Jintaek Park ,  Hansoo Kim ,  Juhyuck Chung ,  Wonseok Cho

    发明人： Sang-Yong Park ,  Jintaek Park ,  Hansoo Kim ,  Juhyuck Chung ,  Wonseok Cho

    IPC分类号： H01L29/66

    CPC分类号： H01L21/823475 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

    摘要： A three dimensional (3D) semiconductor device includes; a vertical channel extending from a lower end proximate a substrate to an upper end and connecting a plurality of memory cells, and a cell array comprising the plurality of cells, wherein the cell array is arranged in a gate stack of layers having a stair-stepped structure disposed on the substrate. The gate stack includes a lower layer including a lower select line coupled to a lower non-memory transistor proximate the lower end, upper layers including conductive lines respectively coupled to an upper non-memory transistor proximate the upper end and connected as a single conductive piece to form an upper select line, and intermediate layers respectively including a word line and coupled to a cell transistor, wherein the intermediate layers are disposed between the lower select line and the upper select line.

    摘要翻译： 三维（3D）半导体器件包括： 垂直通道，其从靠近基板的下端延伸到上端并连接多个存储单元;以及包括所述多个单元的单元阵列，其中所述单元阵列布置在具有台阶的层的栅堆叠中 结构设置在基板上。 栅极堆叠包括下层，其包括耦合到靠近下端的下部非存储晶体管的下部选择线，上层包括分别耦合到靠近上端的上部非存储晶体管的导线，并作为单个导电片连接 以形成上部选择线，以及分别包括字线并耦合到单元晶体管的中间层，其中中间层设置在下部选择线和上部选择线之间。

    Nonvolatile memory including memory cell array having three-dimensional structure
    6.
    发明授权
    Nonvolatile memory including memory cell array having three-dimensional structure 有权
    包括具有三维结构的存储单元阵列的非易失性存储器

    公开(公告)号：US08987832B2

    公开(公告)日：2015-03-24

    申请号：US14080823

    申请日：2013-11-15

    申请人： Jintaek Park ,  Youngwoo Park

    发明人： Jintaek Park ,  Youngwoo Park

    IPC分类号： H01L27/088 ,  H01L27/115 ,  H01L27/24 ,  H01L29/423 ,  H01L29/792

    CPC分类号： H01L27/11578 ,  H01L27/11551 ,  H01L27/2481 ,  H01L29/4234 ,  H01L29/792

    摘要： A nonvolatile memory is provided which includes a plurality of channel layers and a plurality of insulation layers alternately stacked on a substrate in a direction perpendicular to the substrate, each of the plurality of channel layers including a plurality of channel films extending along a first direction on a plane parallel with the substrate; a plurality of conductive materials extending from a top of the channel layers and the insulation layers up to a portion adjacent to the substrate in a direction perpendicular to the substrate through areas among channel films of each channel layer; a plurality of information storage films provided between the channel films of the channel layers and the conductive materials; and a plurality of bit lines connected to the channel layers, respectively, wherein the conductive materials, the information storage films, and the channel films of the channel layers form a three-dimensional memory cell array, wherein the conductive materials form a plurality of groups, and wherein a distance between the groups is longer than a distance between conductive materials in each other.

    摘要翻译： 提供了一种非易失性存储器，其包括多个通道层和多个绝缘层，所述多个绝缘层沿垂直于所述衬底的方向交替堆叠在衬底上，所述多个沟道层中的每一个包括沿着第一方向延伸的多个沟道膜 与基板平行的平面; 多个导电材料，其从沟道层的顶部和绝缘层延伸到与基板垂直的方向上的与衬底相邻的部分，通过每个沟道层的沟道膜之间的区域; 设置在沟道层的沟道膜和导电材料之间的多个信息存储膜; 以及分别连接到沟道层的多个位线，其中沟道层的导电材料，信息存储膜和沟道膜形成三维存储单元阵列，其中导电材料形成多个组 并且其中所述组之间的距离长于彼此之间的导电材料之间的距离。

    Three-Dimensional Semiconductor Devices
    9.
    发明申请
    Three-Dimensional Semiconductor Devices 审中-公开
    三维半导体器件

    公开(公告)号：US20160163733A1

    公开(公告)日：2016-06-09

    申请号：US15009040

    申请日：2016-01-28

    申请人： Jintaek Park ,  Youngwoo Park

    发明人： Jintaek Park ,  Youngwoo Park

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11582 ,  G11C5/02 ,  G11C5/063 ,  H01L27/249 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/148

    摘要： A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively.

    摘要翻译： 三维半导体器件包括设置在衬底上的位线，设置在衬底和位线之间的栅极结构，设置在栅极结构和位线之间的公共源极线，以及将位线连接到公共端 源线。 每个通道管可以包括延伸穿过栅极结构的一对垂直部分和连接垂直部分的水平部分。 一对垂直部分分别设置在彼此相邻布置的一对位线下方。

    Three-dimensional semiconductor devices with current path selection structure
    10.
    发明授权
    Three-dimensional semiconductor devices with current path selection structure 有权
    具有电流路径选择结构的三维半导体器件

    公开(公告)号：US09299707B2

    公开(公告)日：2016-03-29

    申请号：US14150452

    申请日：2014-01-08

    申请人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

    发明人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

    IPC分类号： H01L27/108 ,  H01L27/105 ,  H01L27/115 ,  G11C16/10 ,  G11C16/14

    CPC分类号： H01L27/1052 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556

    摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.

    摘要翻译： 提供三维半导体器件及其操作方法。 三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。 所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。 例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。