公开(公告)号：US20100097176A1

公开(公告)日：2010-04-22

申请号：US12647165

申请日：2009-12-24

申请人： Satoshi SAKURAI ,  Nobuo YATSUO ,  Keita HARADA

发明人： Satoshi SAKURAI ,  Nobuo YATSUO ,  Keita HARADA

IPC分类号： G06F7/04 ,  G06F3/041

CPC分类号： G06F3/04883 ,  G06F21/36 ,  G06F21/83

摘要： An input device having a given input screen includes a first unit that generates data indicating any one of a touch position, a touch area, and a touching time, the touch position being a position touched by an object, the touch area being an area touched by the object, and the touching time being a period touched by the object, a second unit that generates password codes based on any one of the touch position, the touch area, and the touching time, and a third unit that judges whether a user is an authorized user based on the password code. It is possible to generate password codes including data of any one of the touch position, the touch area, and the touching time. Accordingly, the password cannot be stolen by others, and the input device with which impersonation or spoofing is difficult and the password need not be input.

摘要翻译： 具有给定输入屏幕的输入装置包括产生指示触摸位置，触摸区域和触摸时间中的任何一个的数据的第一单元，触摸位置是被对象触摸的位置，触摸区域是触摸的区域 并且所述触摸时间是所述对象触摸的时段，所述第二单元基于所述触摸位置，所述触摸区域和所述触摸时间中的任一个生成密码，以及第三单元，其判断用户是否 是基于密码的授权用户。 可以生成包括触摸位置，触摸区域和触摸时间中的任一个的数据的密码。 因此，密码不能被其他人盗取，并且难以进行模拟或欺骗的输入设备，并且不需要输入密码。

公开(公告)号：US20110013058A1

公开(公告)日：2011-01-20

申请号：US12834270

申请日：2010-07-12

申请人： Satoshi SAKURAI ,  Kenichi Nakamura

发明人： Satoshi SAKURAI ,  Kenichi Nakamura

IPC分类号： H04N5/335 ,  H03M3/00

CPC分类号： H04N5/37455 ,  H03M1/1019 ,  H03M1/123 ,  H03M1/56 ,  H04N5/3575

摘要： Certain embodiments provide an ADC includes a comparator, a binary counter and a control circuit. The comparator compares a first analog signal voltage with a first reference voltage, and compares a second analog signal voltage with a second reference voltage. The binary counter counts up the clock signal for a first period until the first reference voltage becomes equal to the first analog signal after the comparator starts to compare the first reference voltage with the first analog signal voltage, and inverts a logic level of the count output having a plurality of bits after the first period elapses. The binary counter counts up the clock signal for a second period until the second reference voltage becomes equal to a second analog signal after the comparator starts to compare the second reference voltage with the second analog signal voltage.

摘要翻译： 某些实施例提供的ADC包括比较器，二进制计数器和控制电路。 比较器将第一模拟信号电压与第一参考电压进行比较，并将第二模拟信号电压与第二参考电压进行比较。 二进制计数器对第一周期的时钟信号进行计数，直到比较器开始比较第一参考电压和第一模拟信号电压之后，第一参考电压变为等于第一模拟信号，并且反转计数输出的逻辑电平 在经过第一时间段之后具有多个位。 在比较器开始比较第二参考电压和第二模拟信号电压之后，二进制计数器对时钟信号计数第二个周期，直到第二参考电压变为等于第二模拟信号。

公开(公告)号：US20080237736A1

公开(公告)日：2008-10-02

申请号：US11964217

申请日：2007-12-26

申请人： Satoshi SAKURAI ,  Satoshi Goto ,  Toru FUJIOKA

发明人： Satoshi SAKURAI ,  Satoshi Goto ,  Toru FUJIOKA

IPC分类号： H01L27/06

CPC分类号： H01L27/088 ,  H01L21/823425 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0635 ,  H01L2223/6644 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01P5/184 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.

摘要翻译： 提供了一种能够促进移动电话等中使用的RF功率模块的小型化的技术。 定向耦合器形成在其中形成RF功率模块的放大部分的半导体芯片内部。 定向耦合器的子线形成在与作为半导体芯片的放大部分的LDMOSFET的漏极区域的漏极线相同的层中。 由此，预定的漏极线用作主线，并且定向耦合器与主线一起经由绝缘膜与由主线平行布置的子线构成。

公开(公告)号：US20120132786A1

公开(公告)日：2012-05-31

申请号：US13234453

申请日：2011-09-16

申请人： Akiko Mori ,  Satoshi SAKURAI

发明人： Akiko Mori ,  Satoshi SAKURAI

IPC分类号： H01L27/146

CPC分类号： H04N5/355 ,  H04N5/3742 ,  H04N5/3745

摘要： According to one embodiment, a solid state imaging device includes a pixel cell including an FD node to convert a charge stored in a photodiode into a signal voltage and an amplifier transistor in which a gate is connected to the FD node, a source is connected to an output signal line, and a drain is connected to a pixel-power node, a voltage control portion including a first control transistor in which a gate sets to a first bias voltage, a source is connected to the output signal line, and a drain is connected to a first control portion-power node, a load circuit including a current source connected directly between one end of the output signal line and a source power supply node, and a control circuit which controls an operation to decide a reset voltage of the output signal line. The control circuit boosts the FD node.

摘要翻译： 根据一个实施例，固态成像装置包括像素单元，其包括用于将存储在光电二极管中的电荷转换为信号电压的FD节点和其中栅极连接到FD节点的放大器晶体管，源极连接到 输出信号线和漏极连接到像素功率节点，电压控制部分包括第一控制晶体管，栅极设置为第一偏置电压，源极连接到输出信号线，漏极 连接到第一控制部分电力节点，负载电路包括直接连接在输出信号线的一端和源电源节点之间的电流源，以及控制电路，其控制用于决定所述输出信号线的复位电压的操作 输出信号线。 控制电路提升FD节点。

公开(公告)号：US20100238335A1

公开(公告)日：2010-09-23

申请号：US12723901

申请日：2010-03-15

申请人： Satoshi SAKURAI

发明人： Satoshi SAKURAI

IPC分类号： H04N5/335 ,  H03L5/00

CPC分类号： H04N5/3598 ,  H04N5/378

摘要： A clamp circuit includes a clamp circuit which limits an output of a source follower circuit, includes a first Nch transistor, a first constant current source connected between ground and the output terminal, a second Nch transistor having a gate that receives a bias voltage and a source connected to the output terminal of the source follower circuit, a second constant current source connected between the power supply and a drain of the second Nch transistor, and a first Pch transistor having a gate connected to the drain of the second Nch transistor, a source connected to the power supply, and a drain connected to the output terminal of the source follower circuit.

摘要翻译： 钳位电路包括限制源极跟随器电路的输出的钳位电路，包括第一N沟道晶体管，连接在地和输出端之间的第一恒流源，具有接收偏置电压的栅极的第二N沟道晶体管， 源极连接到源极跟随器电路的输出端子，连接在电源和第二N沟道晶体管的漏极之间的第二恒定电流源和连接到第二N沟道晶体管的漏极的栅极的第一Pch晶体管， 源极连接到电源，并且漏极连接到源极跟随器电路的输出端子。

公开(公告)号：US20100117737A1

公开(公告)日：2010-05-13

申请号：US12575494

申请日：2009-10-08

申请人： Masao KONDO ,  Yoshikuni MATSUNAGA ,  Kenta SEKI ,  Satoshi SAKURAI

发明人： Masao KONDO ,  Yoshikuni MATSUNAGA ,  Kenta SEKI ,  Satoshi SAKURAI

IPC分类号： H03F3/26

CPC分类号： H03F3/193 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49111 ,  H03F1/0272 ,  H03F1/565 ,  H03F3/195 ,  H03F3/21 ,  H03F3/245 ,  H03F3/26 ,  H03F3/265 ,  H03F3/45179 ,  H03F3/45475 ,  H03F3/68 ,  H03F2200/105 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/411 ,  H03F2200/451 ,  H03F2200/465 ,  H03F2200/534 ,  H03F2200/541 ,  H03F2203/45481 ,  H03F2203/45544 ,  H03F2203/45621 ,  H03F2203/45631 ,  H03F2203/45731 ,  H01L2924/00014

摘要： A reduction is achieved in the primary-side input impedance of a transformer (voltage transformer) as an output matching circuit without involving a reduction in Q-factor. An RF power amplifier includes transistors, and a transformer as the output matching circuit. The transformer has a primary coil and a secondary coil which are magnetically coupled to each other. To the input terminals of the transistors, respective input signals are supplied. The primary coil is coupled to each of the output terminals of the transistors. From the secondary coil, an output signal is generated. The primary coil includes a first coil and a second coil which are coupled in parallel between the respective output terminals of the transistors, and each magnetically coupled to the secondary coil. By the parallel coupling of the first and second coils of the primary coil, the input impedance of the primary coil is reduced.

摘要翻译： 在作为输出匹配电路的变压器（电压互感器）的初级侧输入阻抗中实现减小，而不涉及Q因子的降低。 RF功率放大器包括晶体管和变压器作为输出匹配电路。 变压器具有彼此磁耦合的初级线圈和次级线圈。 对于晶体管的输入端，提供相应的输入信号。 初级线圈耦合到晶体管的每个输出端子。 从次级线圈产生输出信号。 初级线圈包括第一线圈和第二线圈，它们并联耦合在晶体管的相应输出端之间，并且每一个磁耦合到次级线圈。 通过初级线圈的第一和第二线圈的并联耦合，初级线圈的输入阻抗减小。

公开(公告)号：US20130056730A1

公开(公告)日：2013-03-07

申请号：US13666248

申请日：2012-11-01

申请人： Satoshi SAKURAI ,  Satoshi GOTO ,  Toru FUJIOKA

发明人： Satoshi SAKURAI ,  Satoshi GOTO ,  Toru FUJIOKA

IPC分类号： H01L25/16

CPC分类号： H01L27/088 ,  H01L21/823425 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0635 ,  H01L2223/6644 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01P5/184 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.

摘要翻译： 提供了一种能够促进移动电话等中使用的RF功率模块的小型化的技术。 定向耦合器形成在其中形成RF功率模块的放大部分的半导体芯片内部。 定向耦合器的子线形成在与作为半导体芯片的放大部分的LDMOSFET的漏极区域的漏极线相同的层中。 由此，预定的漏极线用作主线，并且定向耦合器与主线一起经由绝缘膜与由主线平行布置的子线构成。

公开(公告)号：US20120229217A1

公开(公告)日：2012-09-13

申请号：US13398893

申请日：2012-02-17

申请人： Takayuki KAWANO ,  Kenta SEKI ,  Satoshi SAKURAI

发明人： Takayuki KAWANO ,  Kenta SEKI ,  Satoshi SAKURAI

IPC分类号： H03F3/68

CPC分类号： H03F1/565 ,  H03F1/0261 ,  H03F1/0277 ,  H03F3/195 ,  H03F3/211 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/18 ,  H03F2200/222 ,  H03F2200/318 ,  H03F2200/336 ,  H03F2200/387 ,  H03F2200/411 ,  H03F2203/7206 ,  H03F2203/7236

摘要： There is a need to provide a high-frequency power amplifier capable of reducing a talk current and reducing a phase deviation in output. The high-frequency power amplifier includes differently sized first through fifth power amplification transistors and impedance matching circuits for example. The high-frequency power amplifier changes a signal path to be used in accordance with a power specification signal. The high-frequency power amplifier uses a signal path from the first transistor to the second transistor in high power mode. The high-frequency power amplifier uses a signal path from the first transistor to the third transistor in medium power mode. The high-frequency power amplifier uses a signal path from the fourth transistor to the fifth transistor in low power mode. The high-frequency power amplifier is configured so that each of the signal paths includes the same number of stages of power amplification transistors and impedance matching circuits.

摘要翻译： 需要提供能够降低通话电流并减少输出的相位偏差的高频功率放大器。 高频功率放大器包括例如不同尺寸的第一至第五功率放大晶体管和阻抗匹配电路。 高频功率放大器根据功率规格信号改变要使用的信号路径。 高频功率放大器在高功率模式下使用从第一晶体管到第二晶体管的信号路径。 高频功率放大器在中等功率模式下使用从第一晶体管到第三晶体管的信号路径。 高频功率放大器在低功率模式下使用从第四晶体管到第五晶体管的信号路径。 高频功率放大器被配置为使得每个信号路径包括相同级数的功率放大晶体管和阻抗匹配电路。

公开(公告)号：US20100103017A1

公开(公告)日：2010-04-29

申请号：US12606283

申请日：2009-10-27

申请人： Satoshi SAKURAI

发明人： Satoshi SAKURAI

IPC分类号： H03M1/12

CPC分类号： H03M1/1023 ,  H03M1/002 ,  H03M1/1295 ,  H03M1/56

摘要： An analog-to-digital converter receives first and second analog signal voltages, and first and second comparison voltages. The first and second comparison voltages decrease by the same fixed inclination from a first reference voltage to below the first signal voltage and from a second reference voltage to below the second signal voltage, respectively. The converter counts cumulatively over first periods to acquire a first result, counts cumulatively over second periods to acquire a second result, and outputs a difference between the first and second results as a digital quantity. Each first period is time required for the first comparison voltage to change from the first reference voltage to the same voltage as the first signal voltage. Each second period is time required for the second comparison voltage to change from the second reference voltage to the same voltage as the second signal voltage.

摘要翻译： 模拟 - 数字转换器接收第一和第二模拟信号电压以及第一和第二比较电压。 第一和第二比较电压分别从第一参考电压降低到低于第一信号电压并从第二参考电压降低到第二信号电压以下相同的固定倾斜度。 转换器在第一时段累积计数以获取第一结果，累积地在第二周期上计数以获得第二结果，并将第一和第二结果之间的差输出为数字量。 每个第一周期是第一比较电压从第一参考电压变为与第一信号电压相同的电压所需的时间。 每个第二周期是第二比较电压从第二参考电压变为与第二信号电压相同的电压所需的时间。