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    Electronic Devices and Systems, and Methods for Making and Using the Same
    5.
    发明申请
    Electronic Devices and Systems, and Methods for Making and Using the Same 有权
    电子设备和系统及其制造和使用方法

    公开(公告)号：US20110074498A1

    公开(公告)日：2011-03-31

    申请号：US12708497

    申请日：2010-02-18

    申请人： Scott E. Thompson ,  Damodar R. Thummalapally

    发明人： Scott E. Thompson ,  Damodar R. Thummalapally

    IPC分类号： G05F1/10 ,  H01L29/78 ,  H01L21/336 ,  H01L27/088 ,  H01L21/8236

    CPC分类号： H01L29/1083 ,  H01L21/0262 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/0921 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1079 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7838

    摘要： A suite of novel structures and methods is provided to reduce power consumption in a wide array of electronic devices and systems. Some of these structures and methods can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. As will be discussed, some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. There are many ways to configure the DDC to achieve different benefits, and additional structures and methods presented herein can be used alone or in conjunction with the DDC to yield additional benefits.

    摘要翻译： 提供了一套新颖的结构和方法，以减少广泛的电子设备和系统的功耗。 这些结构和方法中的一些可以通过重用现有的大量CMOS工艺流程和制造技术来实现，从而允许半导体行业以及更广泛的电子行业避免代替替代技术的成本高昂的风险。 如将要讨论的，一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许具有掺杂剂的FET的阈值电压VT 要更精确地设置通道区域。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 配置DDC以实现不同的好处有许多方法，本文中提供的其他结构和方法可以单独使用或与DDC结合使用，以产生额外的好处。

    Porting a circuit design from a first semiconductor process to a second semiconductor process
    6.
    发明授权
    Porting a circuit design from a first semiconductor process to a second semiconductor process 有权

    公开(公告)号：US08645878B1

    公开(公告)日：2014-02-04

    申请号：US13592122

    申请日：2012-08-22

    申请人： Lawrence T. Clark ,  Scott E. Thompson ,  Richard S. Roy ,  Samuel Leshner

    发明人： Lawrence T. Clark ,  Scott E. Thompson ,  Richard S. Roy ,  Samuel Leshner

    IPC分类号： G06F17/50

    CPC分类号： H01L21/22 ,  G06F17/505 ,  H01L21/266 ,  H01L29/7816

    摘要： Porting a first integrated circuit design targeted for implementation in a first semiconductor manufacturing process, and implementing a second circuit design in a second semiconductor manufacturing process wherein the electrical performance of the second integrated circuit meets or exceeds the requirements of the first integrated circuit design even if the threshold voltage targets of the second integrated circuit design are different from those of the first integrated circuit design; and wherein physical layouts, and in particular the gate-widths and gate-lengths of the transistors, of the first and second integrated circuit designs are the same or substantially the same. The second integrated circuit design, when fabricated in the second semiconductor manufacturing process and then operated, experiences less off-state transistor leakage current than does the first integrated circuit design, when fabricated in the first semiconductor manufacturing process, and then operated. Porting includes determining processing targets for the second semiconductor manufacturing process.

    ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME
    10.
    发明申请
    ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME 有权
    电子设备和系统，以及制造和使用它们的方法

    公开(公告)号：US20120299111A1

    公开(公告)日：2012-11-29

    申请号：US13553593

    申请日：2012-07-19

    申请人： Scott E. Thompson ,  Damodar R. Thummalapally

    发明人： Scott E. Thompson ,  Damodar R. Thummalapally

    IPC分类号： H01L29/78 ,  H01L27/092

    CPC分类号： H01L29/1083 ,  H01L21/0262 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823807 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/0921 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0653 ,  H01L29/105 ,  H01L29/1079 ,  H01L29/66545 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7838

    摘要： Some structures and methods to reduce power consumption in devices can be implemented largely by reusing existing bulk CMOS process flows and manufacturing technology, allowing the semiconductor industry as well as the broader electronics industry to avoid a costly and risky switch to alternative technologies. Some of the structures and methods relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced σVT compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. Additional structures, configurations, and methods presented herein can be used alone or in conjunction with the DDC to yield additional and different benefits.

    摘要翻译： 减少设备功耗的一些结构和方法可以通过重用现有的大量CMOS工艺流程和制造技术来实现，从而允许半导体行业以及更广泛的电子行业避免成本高昂的风险转换到替代技术。 一些结构和方法涉及深度消耗通道（DDC）设计，允许基于CMOS的器件与常规体CMOS相比具有减小的VT，并且可以允许在沟道区中具有掺杂剂的FET的阈值电压VT为 设置得更精确。 与传统的体积CMOS晶体管相比，DDC设计也可以具有强大的机身效应，可以显着地动态控制DDC晶体管的功耗。 本文提供的其他结构，配置和方法可以单独使用或与DDC结合使用，以产生额外和不同的益处。