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    Method of manufacturing transistor having recessed channel
    3.
    发明授权
    Method of manufacturing transistor having recessed channel 失效
    制造具有凹槽的晶体管的方法

    公开(公告)号：US07125774B2

    公开(公告)日：2006-10-24

    申请号：US10937532

    申请日：2004-09-08

    申请人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

    发明人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

    IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/3205

    CPC分类号： H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7835

    摘要： A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

    摘要翻译： 提供一种制造具有凹槽的晶体管的方法。 该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部， 沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

    Method of manufacturing transistor having recessed channel
    4.
    发明申请
    Method of manufacturing transistor having recessed channel 失效
    制造具有凹槽的晶体管的方法

    公开(公告)号：US20050054163A1

    公开(公告)日：2005-03-10

    申请号：US10937532

    申请日：2004-09-08

    申请人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

    发明人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78

    CPC分类号： H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7835

    摘要： A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

    摘要翻译： 提供一种制造具有凹槽的晶体管的方法。 该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部， 沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

    Gap-fill method using high density plasma chemical vapor deposition process and method of manufacturing integrated circuit device
    7.
    发明申请
    Gap-fill method using high density plasma chemical vapor deposition process and method of manufacturing integrated circuit device 审中-公开
    使用高密度等离子体化学气相沉积工艺的间隙填充方法和制造集成电路器件的方法

    公开(公告)号：US20050136686A1

    公开(公告)日：2005-06-23

    申请号：US11015095

    申请日：2004-12-16

    申请人： Do-Hyung Kim ,  Hyeon-Deok Lee ,  Ju-Bum Lee

    发明人： Do-Hyung Kim ,  Hyeon-Deok Lee ,  Ju-Bum Lee

    IPC分类号： H01L21/205 ,  H01L21/316 ,  H01L21/762 ,  H01L21/768 ,  H01L21/76 ,  H01L21/469

    CPC分类号： H01L21/02164 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/31612 ,  H01L21/76229 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76837

    摘要： A method of filling gaps in an integrated circuit device is provided, that is less likely to fill voids and does not cause a lung defect. In one embodiment, a method of manufacturing an integrated circuit device including the gap filling method includes: etching a predetermined area of an integrated circuit device to form a trench, filling the trench with a high density plasma oxide by performing an HDP-CVD process using a first process gas including comprising a gas containing an element from the fluorine group, silane gas, and oxygen to form a high density plasma oxide layer, and plasma treating the integrated circuit substrate with a second process gas including a hydrogen gas or hydrogen and oxygen gases.

    摘要翻译： 提供了一种填充集成电路装置中的间隙的方法，其不太可能填充空隙并且不引起肺部缺陷。 在一个实施例中，制造包括间隙填充方法的集成电路器件的方法包括：蚀刻集成电路器件的预定区域以形成沟槽，通过使用HDP-CVD工艺使用高密度等离子体氧化物填充沟槽 包括含有来自氟基团的元素的气体，硅烷气体和氧气以形成高密度等离子体氧化物层的第一工艺气体，以及用包括氢气或氢气和氧气的第二工艺气体等离子体处理集成电路衬底 气体。