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    Flip chip optical semiconductor on a PCB
    1.
    发明授权
    Flip chip optical semiconductor on a PCB 有权
    在PCB上倒装芯片光学半导体

    公开(公告)号：US06984866B1

    公开(公告)日：2006-01-10

    申请号：US10391283

    申请日：2003-03-17

    申请人： Shahram Mostafazadeh ,  Joseph O. Smith ,  Matthew D. Penry

    发明人： Shahram Mostafazadeh ,  Joseph O. Smith ,  Matthew D. Penry

    IPC分类号： H01L31/0203

    CPC分类号： H01L31/0203 ,  H01L27/14618 ,  H01L2924/15192

    摘要： Semiconductor devices and methods for making semiconductor devices. The present invention allows a flip chip assembly to be used with an optical semiconductor device. The optical semiconductor flip chip is positioned over a hole in a PCB such that the imaging area of the optical semiconductor flip chip faces the hole. The hole allows the imaging area to be unobstructed by the PCB. Underfill material can be prevented from going into the hole by erecting a barrier on top of the PCB that surrounds the hole.

    摘要翻译： 用于制造半导体器件的半导体器件和方法。 本发明允许与光学半导体器件一起使用倒装芯片组件。 光学半导体倒装芯片位于PCB中的孔的上方，使得光学半导体倒装芯片的成像区域面向孔。 该孔允许成像区域被PCB阻挡。 可以通过在围绕孔的PCB的顶部上竖立阻挡层来防止底部填充材料进入孔中。

    Lead frame chip scale package
    4.
    发明授权
    Lead frame chip scale package 有权
    引线框架芯片级封装

    公开(公告)号：US06888228B1

    公开(公告)日：2005-05-03

    申请号：US09625071

    申请日：2000-07-25

    申请人： Shahram Mostafazadeh ,  Joseph O. Smith

    发明人： Shahram Mostafazadeh ,  Joseph O. Smith

    IPC分类号： H01L21/56 ,  H01L21/68 ,  H01L23/24 ,  H01L23/495

    CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L23/24 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/0101 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

    摘要： In one aspect of the invention, a lead frame panel suitable for use in packaging an array of integrated circuits is described. The lead frame panel includes a matrix of tie bars that extend in substantially perpendicular rows and columns to define a two dimensional array of immediately adjacent device areas separated only by the tie bars. Each device area is suitable for use in an independent integrated circuit package and includes a die attach pad and a plurality of conductive contacts. In another aspect of the invention, a panel assembly suitable for use in simultaneously packaging a multiplicity of integrated circuits is described. The panel assembly includes a lead frame panel formed from a conductive sheet. The lead frame panel is patterned to define at least one two dimensional array of adjacent device areas. Each device area is suitable for use as part of an independent integrated circuit package and including a die and a plurality of contacts positioned around and electrically connected to the die. A molded cap is also provided that substantially uniformly covers a two dimensional array of adjacent device areas while leaving bottom surfaces of the conductive contacts exposed to facilitate electrical connection to external components. The encapsulation material that forms the molded cap is exposed at a bottom surface of the panel of integrated circuits to physically isolate the contacts.

    摘要翻译： 在本发明的一个方面，描述了适用于封装集成电路阵列的引线框架面板。 引线框架面板包括一系列连接杆，其基本垂直的行和列延伸，以限定仅由连接杆分离的紧邻设备区域的二维阵列。 每个器件区域适用于独立的集成电路封装，并且包括管芯附接焊盘和多个导电触点。 在本发明的另一方面，描述了适用于同时封装多个集成电路的面板组件。 面板组件包括由导电片形成的引线框架面板。 图案化引线框架面板以限定相邻设备区域的至少一个二维阵列。 每个器件区域适合用作独立集成电路封装的一部分，并且包括管芯和定位在芯片周围并电连接到管芯的多个触点。 还提供了模制盖，其基本上均匀地覆盖相邻设备区域的二维阵列，同时使导电触头的底表面暴露以促进与外部组件的电连接。 形成模制帽的封装材料暴露在集成电路板的底表面以物理地隔离触点。

    Chip sized package
    6.
    发明授权
    Chip sized package 失效
    芯片尺寸封装

    公开(公告)号：US6054772A

    公开(公告)日：2000-04-25

    申请号：US70111

    申请日：1998-04-29

    申请人： Shahram Mostafazadeh ,  Joseph O. Smith

    发明人： Shahram Mostafazadeh ,  Joseph O. Smith

    IPC分类号： H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/3107 ,  H01L2224/1134 ,  H01L2224/94

    摘要： An improved wafer based packaging arrangement for integrated circuits is disclosed. In one aspect of the invention, external contacts are formed for the packaged integrated circuits by contact studs formed from bonding wires. One end of each contact studs is ball bonded to an associated wafer bond pad. An elongated portion of each wire (contact stud) extends outward the wafer surface and terminates at a second end that forms an external contact. Filling material surrounds a significant portion of the contact studs to hold the studs in place but leaves at least a portion of the second ends exposed to form external contacts. In some embodiments, the external contacts are substantially coplanar with the surface of the filling material, while in others, a protrusion beyond the filling material surface is left to form a contact bump. The wafers are eventually diced to form discrete packaged integrated circuits having external contacts formed by the contact studs.

    摘要翻译： 公开了用于集成电路的改进的基于晶片的封装装置。 在本发明的一个方面，通过由接合线形成的接触柱形成用于封装的集成电路的外部接触。 每个接触螺柱的一端球焊接到相关联的晶片接合焊盘。 每个线（接触柱）的细长部分向外延伸晶片表面，并终止于形成外部接触的第二端。 填充材料围绕接触柱的重要部分以将螺柱保持在适当的位置，但是将第二端的至少一部分暴露以形成外部接触。 在一些实施例中，外部触点与填充材料的表面基本上共面，而在另一些实施例中，留下超过填充材料表面的突起形成接触凸块。 最终切割晶片以形成具有由接触柱形成的外部触头的分立的封装集成电路。

    Apparatus and method for force mounting semiconductor packages to printed circuit boards
    9.
    发明授权
    Apparatus and method for force mounting semiconductor packages to printed circuit boards 有权
    将半导体封装强制安装到印刷电路板的装置和方法

    公开(公告)号：US07171745B2

    公开(公告)日：2007-02-06

    申请号：US10956200

    申请日：2004-09-30

    申请人： Shahram Mostafazadeh ,  Joseph O. Smith

    发明人： Shahram Mostafazadeh ,  Joseph O. Smith

    IPC分类号： H05K3/30

    CPC分类号： H05K3/325 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K2201/10121 ,  H05K2201/10234 ,  H05K2201/10719 ,  H05K2201/10734 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49144 ,  Y10T29/49208 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  H01L2924/00012 ,  H01L2924/00

    摘要： An apparatus and method for force mounting semiconductor packages onto printed circuit boards without the use of solder. The apparatus includes a substrate, a first integrated circuit die mounted onto the substrate, a housing configured to house the first integrated circuit die mounted onto the substrate, and a force mechanism configured to force mount the housing including the integrated circuit die and substrate onto a printed circuit board. The method includes mounting a first integrated circuit die onto a first surface of a substrate, housing the first integrated circuit die mounted onto the substrate in a housing, and using a force mechanism to force mount the housing including the first integrated circuit die mounted on the substrate onto a printed circuit board. According to various embodiments, the force mechanism includes one of the following types of force mechanisms clamps, screws, bolts, adhesives, epoxy, or Instrument housings or heat stakes.

    摘要翻译： 一种在不使用焊料的情况下将半导体封装强制安装到印刷电路板上的装置和方法。 该装置包括基板，安装在基板上的第一集成电路芯片，被构造成容纳安装在基板上的第一集成电路芯片的壳体，以及强制机构，其被构造成将包括集成电路管芯和基板的壳体安装到 印刷电路板。 该方法包括将第一集成电路管芯安装到衬底的第一表面上，将安装在衬底上的第一集成电路管芯容纳在壳体中，并且使用力机构来强制安装壳体，该壳体包括安装在衬底上的第一集成电路管芯 衬底到印刷电路板上。 根据各种实施例，力机构包括以下类型的力机构夹具，螺钉，螺栓，粘合剂，环氧树脂或仪器壳体或热桩中的一种。