公开(公告)号：US09099556B2

公开(公告)日：2015-08-04

申请号：US13213409

申请日：2011-08-19

申请人： Chen-Liang Chu ,  Fei-Yuh Chen ,  Yi-Sheng Chen ,  Shih-Kuang Hsiao ,  Chun Lin Tsai ,  Kong-Beng Thei

发明人： Chen-Liang Chu ,  Fei-Yuh Chen ,  Yi-Sheng Chen ,  Shih-Kuang Hsiao ,  Chun Lin Tsai ,  Kong-Beng Thei

IPC分类号： H01L29/76 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/41775 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/78 ,  H01L29/7823 ,  H01L29/7835

摘要： A semiconductor device includes an active region having a channel region and at least a wing region adjoining the channel region under the gate dielectric layer. The at least one wing region may be two symmetrical wing regions across the channel region.

摘要翻译： 半导体器件包括具有通道区域的有源区域和与栅极介电层下方的沟道区域邻接的至少一个翼区域。 所述至少一个机翼区域可以是穿过所述通道区域的两个对称翼区域。

公开(公告)号：US08673712B2

公开(公告)日：2014-03-18

申请号：US13554880

申请日：2012-07-20

申请人： Shih-Kuang Hsiao ,  Chen-Liang Chu ,  Yi-Sheng Chen ,  Fei-Yuh Chen ,  Kong-Beng Thei

发明人： Shih-Kuang Hsiao ,  Chen-Liang Chu ,  Yi-Sheng Chen ,  Fei-Yuh Chen ,  Kong-Beng Thei

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66492 ,  H01L21/761 ,  H01L29/1083 ,  H01L29/66575 ,  H01L29/7833

摘要： Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary well and a counter implant region implanted in the primary well and between the drift drain and the buried layer. The primary well may comprise a first and second implant region with the second implant region at a depth less than the first. The counter implant may be at a depth between the first and second implant regions. The primary well and counter implant region may comprise dopants of the same conductivity type, or both p+-type dopants. A gate may be formed over a portion of a drift drain.

摘要翻译： 这里呈现的是场效应晶体管器件，可选地是侧向功率晶体管及其形成方法，包括提供衬底，产生掺杂掩埋层，以及在掩埋层上的衬底中产生初级阱。 可以在主阱中产生漂移漏极，并且在初级阱中以及漂移漏极和埋层之间注入计数器注入区域。 主阱可以包括第一和第二注入区域，其中第二注入区域的深度小于第一注入区域。 计数器植入物可以处于第一和第二植入区域之间的深度。 主阱和计数器注入区域可以包括相同导电类型的掺杂剂，或者两种p +型掺杂剂。 栅极可以形成在漂移漏极的一部分上。

公开(公告)号：US20140021539A1

公开(公告)日：2014-01-23

申请号：US13554880

申请日：2012-07-20

申请人： Shih-Kuang Hsiao ,  Chen-Liang Chu ,  Yi-Sheng Chen ,  Fei-Yun Chen ,  Kong-Beng Thei

发明人： Shih-Kuang Hsiao ,  Chen-Liang Chu ,  Yi-Sheng Chen ,  Fei-Yun Chen ,  Kong-Beng Thei

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66492 ,  H01L21/761 ,  H01L29/1083 ,  H01L29/66575 ,  H01L29/7833

摘要： Presented herein is a field effect transistor device, optionally a lateral power transistor, and a method for forming the same, comprising providing a substrate, creating a doped buried layer, and creating a primary well in the substrate on the buried layer. A drift drain may be created in the primary well and a counter implant region implanted in the primary well and between the drift drain and the buried layer. The primary well may comprise a first and second implant region with the second implant region at a depth less than the first. The counter implant may be at a depth between the first and second implant regions. The primary well and counter implant region may comprise dopants of the same conductivity type, or both p+-type dopants. A gate may be formed over a portion of a drift drain.

摘要翻译： 这里呈现的是场效应晶体管器件，可选地是侧向功率晶体管及其形成方法，包括提供衬底，产生掺杂掩埋层，以及在掩埋层上的衬底中产生初级阱。 可以在主阱中产生漂移漏极，并且在初级阱中以及漂移漏极和埋层之间注入计数器注入区域。 主阱可以包括第一和第二注入区域，其中第二注入区域的深度小于第一注入区域。 计数器植入物可以处于第一和第二植入区域之间的深度。 主阱和计数器注入区域可以包括相同导电类型的掺杂剂，或者两种p +型掺杂剂。 栅极可以形成在漂移漏极的一部分上。

公开(公告)号：US09054025B2

公开(公告)日：2015-06-09

申请号：US12478135

申请日：2009-06-04

申请人： Su-Chen Lai ,  Kong-Beng Thei ,  Harry Chuang ,  Gary Shen ,  Shun-Jang Liao

发明人： Su-Chen Lai ,  Kong-Beng Thei ,  Harry Chuang ,  Gary Shen ,  Shun-Jang Liao

IPC分类号： H01L21/66 ,  H01L21/762

CPC分类号： H01L22/20 ,  H01L21/76224 ,  H01L22/12

摘要： A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time.

摘要翻译： 公开了一种用于制造隔离区的台阶高度之间的均匀性提高的集成电路的方法。 该方法包括提供具有一个或多个沟槽的衬底; 填充一个或多个沟槽; 在所述一个或多个填充的沟槽上执行化学机械抛光，其中所述一个或多个填充的沟槽中的每一个包括厚度; 测量所述一个或多个填充沟槽中的每一个的厚度; 基于所测量的一个或多个填充的沟槽中的每一个的厚度来确定进行蚀刻处理的时间量; 并对所确定的时间量进行蚀刻处理。

公开(公告)号：US20120270379A1

公开(公告)日：2012-10-25

申请号：US13538220

申请日：2012-06-29

申请人： Su-Chen Lai ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Hak-Lay Chuang ,  Chiung-Han Yeh ,  Hong-Dyi Chang ,  Kuo Cheng Cheng ,  Chien-Hung Wu ,  Tzung-Chi Lee

发明人： Su-Chen Lai ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Hak-Lay Chuang ,  Chiung-Han Yeh ,  Hong-Dyi Chang ,  Kuo Cheng Cheng ,  Chien-Hung Wu ,  Tzung-Chi Lee

IPC分类号： H01L21/76

CPC分类号： H01L21/823437 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/823828 ,  H01L27/08

摘要： A method of semiconductor device fabrication including forming a plurality of gate structures in a first portion of a substrate, wherein the plurality of gate structures have a first height. A first metal gate structure is formed in a second portion of the substrate, the first metal gate structure being surrounded by an isolation region. A plurality of dummy gate structures is formed in the second portion of the substrate. The plurality of dummy gate structures are configured in a ring formation encircling the metal gate structure and the isolation region. The plurality of dummy structures have a top surface that is substantially planar with the plurality of gate structures and covers at least 5% of a pattern density of the second portion of the substrate.

摘要翻译： 一种半导体器件制造方法，包括在衬底的第一部分中形成多个栅极结构，其中所述多个栅极结构具有第一高度。 第一金属栅极结构形成在衬底的第二部分中，第一金属栅极结构被隔离区包围。 在基板的第二部分中形成多个虚拟栅极结构。 多个虚拟栅极结构被构造成围绕金属栅极结构和隔离区域的环形结构。 多个虚拟结构具有与多个栅极结构基本平面的顶表面，并且覆盖基板的第二部分的图案密度的至少5％。

公开(公告)号：US20120146057A1

公开(公告)日：2012-06-14

申请号：US13399394

申请日：2012-02-17

申请人： Chen-Pin Hsu ,  Kong-Beng Thei ,  Harry Chuang

发明人： Chen-Pin Hsu ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L29/78 ,  H01L29/24

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.

摘要翻译： 本公开提供了一种制造半导体器件的方法，该方法包括在硅衬底上形成栅极叠层，在栅极叠层的侧壁上形成虚设间隔物，各向同性地蚀刻硅衬底以在栅叠层的任一侧上形成凹陷区，形成 在所述凹部区域中的半导体材料，所述半导体材料与所述硅衬底不同，去除所述虚设衬垫，在所述栅极堆叠和所述半导体材料上形成具有氧化物 - 氮化物 - 氧化物构造的间隔层，并蚀刻所述间隔层以形成 栅极叠层的侧壁上的栅极间隔物。

公开(公告)号：US08174091B2

公开(公告)日：2012-05-08

申请号：US12503641

申请日：2009-07-15

申请人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

发明人： Kong-Beng Thei ,  Chung Long Cheng ,  Chung-Shi Liu ,  Harry Chuang ,  Shien-Yang Wu ,  Shi-Bai Chen

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.

摘要翻译： 提出了电熔丝及其形成方法。 在基材上形成第一层导电线。 在第一层导电线上形成通孔。 通孔优选包括阻挡层和导电材料。 在通孔上形成第二层导电线。 第一外部焊盘形成为耦合到第一层导电线。 第二外部焊盘形成为耦合到第二层导电线。 通孔，第一导线和第二导线适于作为电熔丝。 电熔丝可以通过施加电流而烧坏。 优选实施例的垂直结构适合于形成任何层。

公开(公告)号：US08153498B2

公开(公告)日：2012-04-10

申请号：US12401876

申请日：2009-03-11

申请人： Chen-Pin Hsu ,  Chung-Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

发明人： Chen-Pin Hsu ,  Chung-Long Cheng ,  Kong-Beng Thei ,  Harry Chuang

IPC分类号： H01L21/8232

CPC分类号： H01L27/0629 ,  H01L21/82345 ,  H01L27/088 ,  H01L29/66545 ,  Y10S438/926

摘要： A semiconductor device and method for fabricating a semiconductor device protecting a resistive structure in gate replacement processing is disclosed. The method comprises providing a semiconductor substrate; forming at least one gate structure including a dummy gate over the semiconductor substrate; forming at least one resistive structure including a gate over the semiconductor substrate; exposing a portion of the gate of the at least one resistive structure; forming an etch stop layer over the semiconductor substrate, including over the exposed portion of the gate; removing the dummy gate from the at least one gate structure to create an opening; and forming a metal gate in the opening of the at least one gate structure.

摘要翻译： 公开了一种用于制造在栅极替换处理中保护电阻结构的半导体器件的半导体器件和方法。 该方法包括提供半导体衬底; 在半导体衬底上形成包括虚拟栅极的至少一个栅极结构; 在半导体衬底上形成包括栅极的至少一个电阻结构; 暴露所述至少一个电阻结构的栅极的一部分; 在所述半导体衬底上形成蚀刻停止层，包括在所述栅极的暴露部分上方; 从所述至少一个门结构移除所述伪栅极以产生开口; 以及在所述至少一个栅极结构的开口中形成金属栅极。

公开(公告)号：US08093120B2

公开(公告)日：2012-01-10

申请号：US12839994

申请日：2010-07-20

申请人： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

发明人： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

IPC分类号： H01L21/8238

CPC分类号： H01L29/66606 ,  H01L21/823814 ,  H01L21/823871

摘要： A method is provided that includes providing a substrate; forming a transistor in the substrate, the transistor having a dummy gate; forming a dielectric layer over the substrate and transistor; forming a contact feature in the dielectric layer; and after forming the contact feature, replacing the dummy gate of the transistor with a metal gate. An exemplary contact feature is a dual contact.

摘要翻译： 提供了一种提供基板的方法， 在衬底中形成晶体管，晶体管具有虚拟栅极; 在衬底和晶体管上形成介电层; 在介电层中形成接触特征; 并且在形成接触特征之后，用金属栅极替换晶体管的虚拟栅极。 示例性接触特征是双重接触。

公开(公告)号：US08035165B2

公开(公告)日：2011-10-11

申请号：US12341891

申请日：2008-12-22

申请人： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

发明人： Chiung-Han Yeh ,  Ming-Yuan Wu ,  Kong-Beng Thei ,  Harry Chuang ,  Mong-Song Liang

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66606 ,  H01L21/823814 ,  H01L21/823871

摘要： A semiconductor device is provided which includes a semiconductor substrate, a transistor formed on the substrate, the transistor having a gate stack including a metal gate and high-k gate dielectric and a dual first contact formed on the substrate. The dual first contact includes a first contact feature, a second contact feature overlying the first contact feature, and a metal barrier formed on sidewalls and bottom of the second contact feature, the metal barrier layer coupling the first contact feature to the second contact feature.

摘要翻译： 提供一种半导体器件，其包括半导体衬底，形成在衬底上的晶体管，晶体管具有包括金属栅极和高k栅极电介质的栅极堆叠以及形成在衬底上的双重第一接触。 所述双重第一接触包括第一接触特征，覆盖所述第一接触特征的第二接触特征以及形成在所述第二接触特征的侧壁和底部上的金属屏障，所述金属阻挡层将所述第一接触特征耦合到所述第二接触特征。