Apparatus and Method for Increasing Bandwidths of Stacked Dies
    5.
    发明申请
    Apparatus and Method for Increasing Bandwidths of Stacked Dies 有权
    用于增加堆叠模具带宽的装置和方法

    公开(公告)号:US20120250286A1

    公开(公告)日:2012-10-04

    申请号:US13077654

    申请日:2011-03-31

    IPC分类号: H05K7/02

    摘要: A package structure includes a plurality of die carriers identical to each other. The respective features in each of the plurality of die carriers vertically overlap corresponding features in other ones of the plurality of die carriers. Each of the plurality of die carriers includes a plurality of through-substrate vias (TSVs) including a plurality of data buses. The plurality of die carriers is stacked and electrically connected to each other through the plurality of TSVs. The package structure further includes a plurality of device dies. Each of the plurality of device dies is bonded to one of the plurality of die carriers. Each of the plurality of data buses is configured to dedicate to data transmission of one of the plurality of device dies.

    摘要翻译: 封装结构包括彼此相同的多个管芯托架。 多个裸片载体中的每一个中的相应特征垂直地叠加在多个模具载体中的其它模具载体中的相应特征。 多个管芯载体中的每一个都包括多个包括多个数据总线的穿通基板通路(TSV)。 多个管芯载体通过多个TSV堆叠并彼此电连接。 封装结构还包括多个器件管芯。 多个器件管芯中的每一个被结合到多个管芯载体中的一个。 多个数据总线中的每一个被配置为专用于多个器件管芯之一的数据传输。

    Reducing voltage drops in power networks using unused spaces in integrated circuits
    6.
    发明授权
    Reducing voltage drops in power networks using unused spaces in integrated circuits 有权
    降低集成电路中未使用空间的电力网络中的电压降

    公开(公告)号:US08276110B2

    公开(公告)日:2012-09-25

    申请号:US12692184

    申请日:2010-01-22

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068 G06F2217/78

    摘要: A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added.

    摘要翻译: 设计集成电路的方法包括提供包括电力网络的集成电路设计。 提供一种电压降缓解系统,其包括被配置为在电力网络中自动找到源节点和终端节点的电力带增强器。 添加了使用电压降缓解系统的用于电力网络的冗余带,其中冗余带将源节点和终端节点互连。 在添加冗余带的步骤之后,可以添加虚拟图案。

    Reducing Voltage Drops in Power Networks Using Unused Spaces in Integrated Circuits
    7.
    发明申请
    Reducing Voltage Drops in Power Networks Using Unused Spaces in Integrated Circuits 有权
    降低集成电路中未使用空间的电力网络中的电压降

    公开(公告)号:US20110185331A1

    公开(公告)日:2011-07-28

    申请号:US12692184

    申请日:2010-01-22

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5068 G06F2217/78

    摘要: A method of designing an integrated circuit includes providing an integrated circuit design including a power network. A voltage drop mitigation system is provided, which includes a power strap enhancer configured to automatically find a source node and a terminal node in the power network. A redundant strap for the power network using the voltage drop mitigation system is added, wherein the redundant strap interconnects the source node and the terminal node. After the step of adding the redundant strap, dummy patterns may be added.

    摘要翻译: 设计集成电路的方法包括提供包括电力网络的集成电路设计。 提供一种电压降缓解系统,其包括被配置为在电力网络中自动找到源节点和终端节点的电力带增强器。 添加了使用电压降缓解系统的用于电力网络的冗余带,其中冗余带将源节点和终端节点互连。 在添加冗余带的步骤之后,可以添加虚拟图案。

    SiP (system in package) design systems and methods
    8.
    发明授权
    SiP (system in package) design systems and methods 有权
    SiP(系统封装)设计系统和方法

    公开(公告)号:US07565635B2

    公开(公告)日:2009-07-21

    申请号:US11697744

    申请日:2007-04-09

    IPC分类号: G06F17/50 G06F9/45

    CPC分类号: G06F17/5045 G06F2217/40

    摘要: SiP design systems and methods. The system comprises a system partitioning module, a subsystem integration module, a physical design module, and an analysis module. The system partitioning module partitions a target system into subsystem partitions according to partition criteria. The subsystem integration module generates an architecture design and/or a cost estimation for the target system according to the subsystem partitions, at least one SiP platform, and IC geometry data. The physical design module generates a SiP physical design with physical routing for the target system according to the architecture design, the subsystem partitions, the SiP platform, and the IC geometry data. The analysis module performs a performance check within the subsystem partitions based on the SiP physical design and/or simulations of the target system.

    摘要翻译: SiP设计系统和方法。 该系统包括系统分区模块,子系统集成模块,物理设计模块和分析模块。 系统分区模块根据分区标准将目标系统划分为子系统分区。 子系统集成模块根据子系统分区,至少一个SiP平台和IC几何数据生成目标系统的架构设计和/或成本估算。 物理设计模块根据架构设计,子系统分区,SiP平台和IC几何数据,为目标系统生成具有物理路由的SiP物理设计。 分析模块基于SiP物理设计和/或目标系统的模拟来执行子系统分区内的性能检查。

    Bandgap reference apparatus and methods

    公开(公告)号:US09958895B2

    公开(公告)日:2018-05-01

    申请号:US13004617

    申请日:2011-01-11

    IPC分类号: G05F1/10 G05F3/02 G05F3/30

    CPC分类号: G05F3/30

    摘要: Structure and methods for a compensated bandgap reference circuit. A first integrated circuit die having a first bandgap reference circuit with a non-zero temperature coefficient; and having a first output reference signal is provided, a second integrated circuit die having a second bandgap reference circuit with a non-zero temperature coefficient that is of opposite polarity from the temperature coefficient of the first bandgap reference circuit, and having a second output reference signal is provided; an adder circuit disposed on at least one of the first and second integrated circuit dies combines the first and second output reference signals, and outputs a combined reference signal; and connectors for connecting the first and second output signals to the adder circuit are provided. Methods are disclosed for pairing integrated circuit dies with bandgap reference circuits and coupling the dies to form temperature compensated signals.