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24 条记录 (耗时 0.017 秒)

    Apparatus and Method for Increasing Bandwidths of Stacked Dies
    3.
    发明申请
    Apparatus and Method for Increasing Bandwidths of Stacked Dies 有权
    用于增加堆叠模具带宽的装置和方法

    公开(公告)号：US20120250286A1

    公开(公告)日：2012-10-04

    申请号：US13077654

    申请日：2011-03-31

    申请人： Shyh-An Chi ,  Mark Shane Peng

    发明人： Shyh-An Chi ,  Mark Shane Peng

    IPC分类号： H05K7/02

    CPC分类号： H01L23/48 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/0652 ,  H01L2225/06548 ,  H01L2225/06572

    摘要： A package structure includes a plurality of die carriers identical to each other. The respective features in each of the plurality of die carriers vertically overlap corresponding features in other ones of the plurality of die carriers. Each of the plurality of die carriers includes a plurality of through-substrate vias (TSVs) including a plurality of data buses. The plurality of die carriers is stacked and electrically connected to each other through the plurality of TSVs. The package structure further includes a plurality of device dies. Each of the plurality of device dies is bonded to one of the plurality of die carriers. Each of the plurality of data buses is configured to dedicate to data transmission of one of the plurality of device dies.

    摘要翻译： 封装结构包括彼此相同的多个管芯托架。 多个裸片载体中的每一个中的相应特征垂直地叠加在多个模具载体中的其它模具载体中的相应特征。 多个管芯载体中的每一个都包括多个包括多个数据总线的穿通基板通路（TSV）。 多个管芯载体通过多个TSV堆叠并彼此电连接。 封装结构还包括多个器件管芯。 多个器件管芯中的每一个被结合到多个管芯载体中的一个。 多个数据总线中的每一个被配置为专用于多个器件管芯之一的数据传输。

    Fast flip-flop structure with reduced set-up time
    7.
    发明授权
    Fast flip-flop structure with reduced set-up time 有权
    快速的触发器结构，缩短设置时间

    公开(公告)号：US08803581B2

    公开(公告)日：2014-08-12

    申请号：US12758451

    申请日：2010-04-12

    申请人： Shyh-An Chi ,  Shiue Tsong Shen ,  Jeff Lee ,  Frank Y. Lee

    发明人： Shyh-An Chi ,  Shiue Tsong Shen ,  Jeff Lee ,  Frank Y. Lee

    IPC分类号： H03K3/289 ,  H03K3/012

    CPC分类号： H03K3/012 ,  G01R31/318541

    摘要： A flip-flop structure with reduced set-up time is provided. The flip-flop includes the first master latch receiving a function data through the first switch controlled by a clock signal, the second master latch receiving a scan data through the second switch controlled by the clock signal, and a slave latch connected to the first master latch through the third switch controlled by the clock signal. The second master latch is coupled to the first master latch through the fourth switch controlled by the scan enable signal so that the scan enable signal controls whether the function data or the scan data becomes an output from the first master latch to the slave latch, and the slave latch is used to latch and transmit the output from the first master latch.

    摘要翻译： 提供了一种具有缩短设置时间的触发器结构。 触发器包括通过由时钟信号控制的第一开关接收功能数据的第一主锁存器，第二主锁存器通过由时钟信号控制的第二开关接收扫描数据，以及从锁存器连接到第一主器件 通过由时钟信号控制的第三开关锁存。 第二主锁存器通过由扫描使能信号控制的第四开关耦合到第一主锁存器，使得扫描使能信号控制功能数据或扫描数据是否变为从第一主锁存器到从锁存器的输出，以及 从锁存器用于锁存和传输来自第一主锁存器的输出。

    Processor with tightly coupled smart memory unit
    8.
    发明授权
    Processor with tightly coupled smart memory unit 有权
    具有紧耦合智能存储单元的处理器

    公开(公告)号：US08719463B2

    公开(公告)日：2014-05-06

    申请号：US12947177

    申请日：2010-11-16

    申请人： Shyh-An Chi

    发明人： Shyh-An Chi

    IPC分类号： G06F13/28 ,  G06F13/40

    CPC分类号： G06F13/28 ,  G06F12/1081 ,  G06F13/24 ,  G06F13/32 ,  G06F13/4063 ,  G06F15/7821 ,  G06F2212/2532 ,  Y02D10/14 ,  Y02D10/151

    摘要： An information processor includes a central processing unit core and a tightly coupled smart memory unit, the central processing unit core having a direct memory access unit. The tightly coupled smart memory unit having a memory unit coupled to the central processing unit core and a control register, and status register coupled to the central processing unit core and a local processing unit that processes data stored in the memory unit.

    摘要翻译： 信息处理器包括中央处理单元核心和紧密耦合的智能存储器单元，所述中央处理单元核心具有直接存储器存取单元。 紧耦合的智能存储器单元具有耦合到中央处理单元核心的存储单元和控制寄存器，以及耦合到中央处理单元核心的状态寄存器和处理存储在存储器单元中的数据的本地处理单元。

    Dynamic voltage and frequency management in integrated circuits
    9.
    发明申请
    Dynamic voltage and frequency management in integrated circuits 有权

    公开(公告)号：US20080136400A1

    公开(公告)日：2008-06-12

    申请号：US11636171

    申请日：2006-12-07

    申请人： Shyh-An Chi ,  Chih-Hung Chung

    发明人： Shyh-An Chi ,  Chih-Hung Chung

    IPC分类号： G06F1/26 ,  H03K3/03 ,  H03L7/00

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： This invention discloses a system and method for dynamically managing voltage and frequency in an integrated circuit (IC), comprising a plurality of ring oscillators for generating a plurality of continuous pulses with frequencies reflecting the process parameter, operating voltage and temperature effects in the IC, a period generator for generating at least one gating period with a predetermined duration, a plurality of counters coupling to the plurality of ring oscillators as well as the period generator for counting the number of the continuous pulses in the gating period, at least one selector for selecting a predetermined number counted by the plurality of counters, and at least one voltage-and-frequency adjustment circuitry for adjusting one or more operating voltages or one or more clock frequencies in the IC based on the predetermined number selected by the selector, wherein the IC operating voltage or clock frequency correlates with the ring oscillator frequencies.

    Enhanced ESD protection of integrated circuit in 3DIC package
    10.
    发明授权
    Enhanced ESD protection of integrated circuit in 3DIC package 有权
    3DIC封装中集成电路的增强ESD保护

    公开(公告)号：US09412708B2

    公开(公告)日：2016-08-09

    申请号：US13009612

    申请日：2011-01-19

    申请人： Shyh-An Chi

    发明人： Shyh-An Chi

    IPC分类号： H02H9/00 ,  H01L23/60 ,  H01L25/065 ,  H01L23/498 ,  H01L23/50

    CPC分类号： H01L23/60 ,  H01L23/49822 ,  H01L23/50 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/15192 ,  H01L2924/15311

    摘要： Enhanced electrostatic discharge (ESD) protection schemes of an integrated circuit in three-dimensional (3D) integrated circuit (ICs) packages, and methods of forming the same are presented in the disclosure. An array of ESD protection devices can be formed in an interposer and placed under one or a plurality of ICs so that a hard block inside an IC on top of the interposer can be connected to an ESD protection device of the array and is protected from ESD. The ESD protection device cell of the array is connected to a Voltage Regulator Module (VRM) which can be placed inside the interposer, on the surface of the interposer, or on the surface of a printed circuit board (PCB). The ESD protection array is of generic nature and can be used with many kinds of ICs to form a three-dimensional IC package. Further embodiments of ESD protection for 3D IC package is disclosed where an ESD protection device inside a first IC 2 can be shared with another IC 1 to protect a hard block within IC 1.

    摘要翻译： 本发明公开了三维（3D）集成电路（IC）封装中集成电路的增强型静电放电（ESD）保护方案及其形成方法。 ESD保护器件的阵列可以形成在插入器中并放置在一个或多个IC下方，使得内插器顶部的IC内部的硬块可以连接到阵列的ESD保护器件并且被保护免受ESD 。 该阵列的ESD保护器件单元连接到一个稳压器模块（VRM），可以放置在插入器内部，插入表面或印刷电路板（PCB）表面上。 ESD保护阵列具有通用性，可与多种IC一起使用，形成三维IC封装。 公开了用于3D IC封装的ESD保护的其它实施例，其中第一IC 2内部的ESD保护装置可以与另一IC 1共享以保护IC 1内的硬块。