公开(公告)号：US07183162B1

公开(公告)日：2007-02-27

申请号：US11284982

申请日：2005-11-21

Applicant: Steven R. Soss ,  Krishna Parat

Inventor： Steven R. Soss ,  Krishna Parat

IPC: H01L21/8247

CPC classification number: H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a microelectronic non-volatile memory cell, a memory cell formed according to the method, and a system including the memory cell. The method comprises: providing a substrate; providing a pair of spaced apart isolation bodies on the substrate, the isolation bodies including respective raised isolation portions, providing the pair comprising providing a buffer layer on the substrate; providing pillar spacers on side walls of the raised isolation portions; removing the buffer layer after providing the pillar spacers; removing the pillar spacers during removing the buffer layer; providing a tunnel dielectric on the surface of the substrate after removing the buffer layer; providing a floating gate on the tunnel dielectric; reducing a height of the isolation bodies to yield corresponding isolation regions; providing source and drain regions on opposite sides of the floating gate; providing an interpoly dielectric on the floating gate; and providing a control gate on the interpoly dielectric to yield the memory cell.

Abstract translation: 形成微电子非易失性存储单元的方法，根据该方法形成的存储单元和包括存储单元的系统。 该方法包括：提供衬底; 在所述衬底上提供一对间隔开的隔离体，所述隔离体包括相应的凸起隔离部分，提供所述对，包括在所述衬底上提供缓冲层; 在凸起隔离部分的侧壁上提供柱状间隔物; 在提供柱间隔物之后去除缓冲层; 在移除缓冲层期间移除柱状间隔物; 在去除缓冲层之后在衬底的表面上提供隧道电介质; 在隧道电介质上提供浮动栅极; 降低隔离体的高度以产生相应的隔离区; 在浮动栅极的相对侧上提供源极和漏极区域; 在所述浮动栅极上提供互补电介质; 以及在所述互聚电介质上提供控制栅极以产生所述存储单元。

公开(公告)号：US20120117306A1

公开(公告)日：2012-05-10

申请号：US12942152

申请日：2010-11-09

Applicant: Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

Inventor： Shafqat Ahmed ,  Khaled Hasnat ,  Pranav Kalavade ,  Krishna Parat ,  Aaron Yip ,  Mark A. Helm ,  Andrew Bicksler

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/00

CPC classification number: G06F3/0625 ,  G06F3/061 ,  G06F3/0653 ,  G06F3/0665 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/28 ,  G06F2212/2022 ,  G06F2212/224 ,  G06F2212/461 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  Y02D10/14

Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

Abstract translation: 公开了存储器件，用于编程感测标志的方法，用于感测标志的方法和存储器系统。 在一个这样的存储器件中，标志存储器单元阵列的奇数位线与短路连接到动态数据高速缓存。 标记存储单元阵列的偶数位线与动态数据高速缓存断开连接。 当读取主存储单元阵列的偶数页时，同时读取包括标志数据的奇数标志存储单元，以便可以确定主存储单元阵列的奇数页是否已被编程。 如果标志数据指示奇数页未被编程，则可以调整阈值电压窗口以确定感测到的偶数存储单元页的状态。

公开(公告)号：US07835187B2

公开(公告)日：2010-11-16

申请号：US12262410

申请日：2008-10-31

Applicant: Satoru Tamada ,  Neal R Mielke ,  Krishna Parat

Inventor： Satoru Tamada ,  Neal R Mielke ,  Krishna Parat

IPC: G11C11/34

CPC classification number: G11C16/24 ,  G11C16/10 ,  G11C16/3427

Abstract: A method and device using bitline-bitline capacitance between adjacent bitlines to boost seed voltage in a memory device are provided. The method may include a precharge phase, a boost phase, an equalize phase, and a lock in phase. In one embodiment, the method may include boosting the seed voltage twice. The bitlines may be divided into one or more segments.

Abstract translation: 提供了一种使用相邻位线之间的位线位线电容来提高存储器件中的种子电压的方法和装置。 该方法可以包括预充电阶段，升压阶段，均衡阶段和同相锁定。 在一个实施例中，该方法可以包括两次提升种子电压。 位线可以分为一个或多个段。

公开(公告)号：US20090283817A1

公开(公告)日：2009-11-19

申请号：US12165272

申请日：2008-06-30

Applicant: Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Srivardhan Gowda ,  Thomas M. Graettinger ,  Nirmal Ramaswamy

Inventor： Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Srivardhan Gowda ,  Thomas M. Graettinger ,  Nirmal Ramaswamy

IPC: H01L29/788 ,  H01L21/28

CPC classification number: H01L21/28052 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

Abstract: Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.

Abstract translation: 通常描述浮栅结构。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的隧道电介质，以及浮栅结构，其至少包括具有第一电子能级或电子功函数的第一区域或与隧道电介质耦合的载流子捕获效率 以及第二区域，其具有与第一区域耦合的第二电子能级或电子功能函数或载流子捕获效率，其中第一电子能级或电子功函数或载流子捕获效率小于第二电子能级或电子功函数或载流子俘获效率 。 与仅包含多晶硅的浮动栅极结构相比，这种电子器件可以减小浮置栅极结构的厚度或减小通过栅极间电介质或其组合的泄漏电流。

公开(公告)号：US20090001443A1

公开(公告)日：2009-01-01

申请号：US11771482

申请日：2007-06-29

Applicant: Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Rhett T. Brewer ,  Thomas M. Graettinger ,  Nirmal Ramaswamy ,  M. Noel Rocklein

Inventor： Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Rhett T. Brewer ,  Thomas M. Graettinger ,  Nirmal Ramaswamy ,  M. Noel Rocklein

IPC: H01L29/788

CPC classification number: H01L29/513 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/42324 ,  H01L29/4234

Abstract: Disclosed is a non-volatile memory cell. The non-volatile memory cell includes a substrate having an active area. A bottom dielectric layer is disposed over the active area of the substrate which provides tunneling migration to the charge carriers towards the active area. A charge storage node is disposed above the bottom dielectric layer. Further, the non-volatile memory cell includes a plurality of top dielectric layers disposed above the charge storage node. Each of the plurality of top dielectric layers can be tuned with a set of attributes for reducing a leakage current through the plurality of top dielectric layers. Over the plurality of top dielectric layers, a control gate is disposed.

Abstract translation: 公开了一种非易失性存储单元。 非易失性存储单元包括具有有源区的基板。 底部电介质层设置在衬底的有源区上方，其向电荷载流子提供隧道迁移到有源区。 电荷存储节点设置在底部电介质层的上方。 此外，非易失性存储单元包括设置在电荷存储节点上方的多个顶部电介质层。 多个顶部电介质层中的每一个可以用一组属性进行调谐，以减少穿过多个顶部电介质层的漏电流。 在多个顶部电介质层中，设置有控制栅极。

公开(公告)号：US20130258781A1

公开(公告)日：2013-10-03

申请号：US13438331

申请日：2012-04-03

Applicant: Akira Goda ,  Yijie Zhao ,  Krishna Parat

Inventor： Akira Goda ,  Yijie Zhao ,  Krishna Parat

IPC: G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

Abstract: Devices, systems and methods of biasing in memory devices facilitate memory device programming and/or erase operations. In at least one embodiment, a first string of memory cells comprising a selected memory cell and a second string of memory cells are coupled to a common data line and a common source where the data line and the source are biased to substantially the same potential during a programming and/or erase operation performed on one or more of the strings of memory cells.

Abstract translation: 存储器件中的偏置的装置，系统和方法促进存储器件编程和/或擦除操作。 在至少一个实施例中，包括所选择的存储器单元和第二存储单元串的存储器单元的第一串被耦合到公共数据线和公共源，其中数据线和源被偏置到基本上相同的电位 对一个或多个存储器单元串执行编程和/或擦除操作。

公开(公告)号：US08498159B2

公开(公告)日：2013-07-30

申请号：US13465328

申请日：2012-05-07

Applicant: Akira Goda ,  Tomoharu Tanaka ,  Krishna Parat ,  Prashant Damle ,  Shafqat Ahmed

Inventor： Akira Goda ,  Tomoharu Tanaka ,  Krishna Parat ,  Prashant Damle ,  Shafqat Ahmed

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.

Abstract translation: 提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。 根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。 响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。

公开(公告)号：US08331160B2

公开(公告)日：2012-12-11

申请号：US13193192

申请日：2011-07-28

Applicant: Prashant S. Damle ,  Krishna Parat ,  Alessandro Torsi ,  Carlo Musilli ,  Kalpana Vakati ,  Akira Goda

Inventor： Prashant S. Damle ,  Krishna Parat ,  Alessandro Torsi ,  Carlo Musilli ,  Kalpana Vakati ,  Akira Goda

IPC: G11C11/34

CPC classification number: G11C16/3404 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32

Abstract: Some embodiments include methods and devices having a module and memory cells. The module is configured to reduce the amount of electrons in the sources and drains of the memory cells during a programming operation.

Abstract translation: 一些实施例包括具有模块和存储器单元的方法和装置。 该模块被配置为在编程操作期间减少存储器单元的源极和漏极中的电子量。

公开(公告)号：US20120218824A1

公开(公告)日：2012-08-30

申请号：US13465328

申请日：2012-05-07

Applicant: Akira Goda ,  Tomoharu Tanaka ,  Krishna Parat ,  Prashant Damle ,  Shafqat Ahmed

Inventor： Akira Goda ,  Tomoharu Tanaka ,  Krishna Parat ,  Prashant Damle ,  Shafqat Ahmed

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.

Abstract translation: 提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。 根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。 响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。

公开(公告)号：US08174893B2

公开(公告)日：2012-05-08

申请号：US12582458

申请日：2009-10-20

Applicant: Akira Goda ,  Tomoharu Tanaka ,  Krishna Parat ,  Prashant Damle ,  Shafqat Ahmed

Inventor： Akira Goda ,  Tomoharu Tanaka ,  Krishna Parat ,  Prashant Damle ,  Shafqat Ahmed

IPC: G11C11/34

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods, for example, are provided. According to at least one such method, multiple independent semiconductor well regions each having strings of memory cells are independently biased during a programming operation performed on a memory device. Reduced charge leakage may be realized during a programming operation in response to independent well biasing methods.

Abstract translation: 提供了用于编程存储器件的方法，被配置为执行所公开的编程方法的存储器件，以及具有被配置为执行所公开的编程方法的存储器件的存储器系统。 根据至少一种这样的方法，在对存储器件执行的编程操作期间，各自具有存储器单元串的多个独立的半导体阱区被独立地偏置。 响应于独立的井偏置方法，在编程操作期间可以实现减少的电荷泄漏。