公开(公告)号：US20120052635A1

公开(公告)日：2012-03-01

申请号：US13221158

申请日：2011-08-30

申请人： Pil-kyu Kang ,  Gil-heyun Choi ,  Dae-lok Bae ,  Byung-Iyul Park ,  Dong-kak Lee

发明人： Pil-kyu Kang ,  Gil-heyun Choi ,  Dae-lok Bae ,  Byung-Iyul Park ,  Dong-kak Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/76254 ,  H01L21/84 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/1203

摘要： A conductive layer buried-type substrate is disclosed. The substrate includes a silicon oxidation layer bonded to a supporting substrate, an adhesion promotion layer that is formed on the silicon oxidation layer and improves an adhesion between the silicon oxidation layer and a conductive layer, wherein the conductive layer is formed on the adhesion promotion layer and comprises a metal layer, and a single crystal semiconductor layer formed on the conductive layer.

摘要翻译： 公开了一种导电层掩埋型衬底。 基板包括结合到支撑基板的硅氧化层，形成在硅氧化层上的粘合促进层，并且改善硅氧化层和导电层之间的粘附性，其中导电层形成在粘附促进层上 并且包括金属层和形成在导电层上的单晶半导体层。

公开(公告)号：US09530726B2

公开(公告)日：2016-12-27

申请号：US14052691

申请日：2013-10-11

申请人： Kwang-jin Moon ,  Byung-Iyul Park ,  Dong-chan Lim ,  Deok-young Jung ,  Gil-heyun Choi ,  Dae-lok Bae ,  Pil-kyu Kang

发明人： Kwang-jin Moon ,  Byung-Iyul Park ,  Dong-chan Lim ,  Deok-young Jung ,  Gil-heyun Choi ,  Dae-lok Bae ,  Pil-kyu Kang

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a via structure having a top surface with a planar portion and a protrusion portion that is surrounded by the planar portion, and includes a conductive structure including a plurality of conductive lines contacting at least a part of the top surface of the via structure.

摘要翻译： 半导体器件包括具有平面部分的顶表面和由平面部分包围的突出部分的通孔结构，并且包括导电结构，该导电结构包括与通孔的顶表面的至少一部分接触的多条导线 结构体。

公开(公告)号：US20130119547A1

公开(公告)日：2013-05-16

申请号：US13603978

申请日：2012-09-05

申请人： Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-Iyul Park ,  Kwang-jin Moon ,  Kun-sang Park ,  Dong-chan Lim ,  Do-sun Lee

发明人： Su-kyoung Kim ,  Gil-heyun Choi ,  Byung-Iyul Park ,  Kwang-jin Moon ,  Kun-sang Park ,  Dong-chan Lim ,  Do-sun Lee

IPC分类号： H01L23/532 ,  H01L23/498

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2924/13091 ,  H01L2924/00

摘要： An integrated circuit device includes a substrate through which a first through-hole extends, and an interlayer insulating film on the substrate, the interlayer insulating film having a second through-hole communicating with the first through-hole. A Through-Silicon Via (TSV) structure is provided in the first through-hole and the second through-hole. The TSV structure extends to pass through the substrate and the interlayer insulating film. The TSV structure comprises a first through-electrode portion having a top surface located in the first through-hole, and a second through-electrode portion having a bottom surface contacting with the top surface of the first through-electrode portion and extending from the bottom surface to at least the second through-hole. Related fabrication methods are also described.

摘要翻译： 集成电路器件包括：第一通孔延伸穿过的衬底和衬底上的层间绝缘膜，所述层间绝缘膜具有与第一通孔连通的第二通孔。 在第一通孔和第二通孔中设置有硅通孔（TSV）结构。 TSV结构延伸穿过衬底和层间绝缘膜。 TSV结构包括具有位于第一通孔中的顶表面的第一通电极部分和具有与第一贯穿电极部分的顶表面接触并从底部延伸的底表面的第二通电极部分 表面至少到第二通孔。 还描述了相关的制造方法。

公开(公告)号：US20100193902A1

公开(公告)日：2010-08-05

申请号：US12502490

申请日：2009-07-14

申请人： Seung-woo SHIN ,  Byung-Iyul Park ,  Jong-myeong Lee ,  Gil-heyun Choi ,  Jong-ho Yun

发明人： Seung-woo SHIN ,  Byung-Iyul Park ,  Jong-myeong Lee ,  Gil-heyun Choi ,  Jong-ho Yun

IPC分类号： H01L23/525

CPC分类号： H01L23/5258 ,  H01L27/105 ,  H01L27/10894 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided is a semiconductor device including a fuse, in which a insulating layer surrounding the fuse or metal wiring is prevented from being damaged due to the cut of a fuse, which can occur when a repair process is performed. The semiconductor device includes a conductive line formed on a semiconductor layer, a protective layer formed on the conductive line, one or more fuses that are electrically connected to the conductive line, and a fuse protective layer formed on the one or more fuses, and spaced apart from the protective layer.

摘要翻译： 提供了一种包括保险丝的半导体器件，其中防止在保险丝或金属布线周围的绝缘层由于保险丝的切断而被损坏，这在维修过程中可能发生。 半导体器件包括形成在半导体层上的导电线，形成在导电线上的保护层，与导电线电连接的一个或多个保险丝，以及形成在一个或多个保险丝上的保险丝保护层， 除了保护层。

公开(公告)号：US20150102497A1

公开(公告)日：2015-04-16

申请号：US14506930

申请日：2014-10-06

申请人： Jae-Hwa Park ,  Kwang-jin Moon ,  Suk-Chul Bang ,  Byung-Iyul Park ,  Jeong-gi Jin ,  Tae-seong Kim ,  Sung-hee Kang

发明人： Jae-Hwa Park ,  Kwang-jin Moon ,  Suk-Chul Bang ,  Byung-Iyul Park ,  Jeong-gi Jin ,  Tae-seong Kim ,  Sung-hee Kang

IPC分类号： H01L23/48 ,  H01L23/50 ,  H01L21/768 ,  H01L23/485

CPC分类号： H01L23/481 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/485 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/14511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/00

摘要： Integrated circuit (IC) devices are provided including: a first multi-layer wiring structure including a plurality of first wiring layers in a first region of a substrate at different levels and spaced apart from one another, and a plurality of first contact plugs between the plurality of first wiring layers and connected to the plurality of first wiring layers; a through-silicon via (TSV) landing pad including a first pad layer in a second region of the substrate at a same level as that of at least one first wiring layer from among the plurality of first wiring layers, and a second pad layer at a same level as that of at least one first contact plug from among the plurality of first contact plugs and contacts the first pad layer; a second multi-layer wiring structure on the TSV landing pad; and a TSV structure that passes through the substrate and is connected to the second multi-layer wiring structure through the TSV landing pad.

摘要翻译： 提供集成电路（IC）装置，包括：第一多层布线结构，其包括在不同层级并彼此间隔开的基板的第一区域中的多个第一布线层，以及多个第一接触塞 多个第一布线层并连接到多个第一布线层; 贯穿硅通孔（TSV）着陆焊盘，其包括在与所述多个第一布线层中的至少一个第一布线层相同水平的所述基板的第二区域中的第一焊盘层;以及第二焊盘层， 与所述多个第一接触插塞中的至少一个第一接触插塞的水平相同，并接触所述第一衬垫层; TSV着陆板上的第二层多层布线结构; 以及TSV结构，其通过所述基板，并且通过所述TSV着陆焊盘与所述第二多层布线结构连接。

公开(公告)号：US09735090B2

公开(公告)日：2017-08-15

申请号：US14873453

申请日：2015-10-02

申请人： Ju-il Choi ,  Atsushi Fujisaki ,  Byung-Iyul Park ,  Ji-soon Park ,  Joo-hee Jang ,  Jeong-gi Jin

发明人： Ju-il Choi ,  Atsushi Fujisaki ,  Byung-Iyul Park ,  Ji-soon Park ,  Joo-hee Jang ,  Jeong-gi Jin

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L23/3135 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L24/00 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/05564 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/11825 ,  H01L2224/11906 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13552 ,  H01L2224/13566 ,  H01L2224/1357 ,  H01L2224/13644 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/01015 ,  H01L2924/014 ,  H01L2924/01074

摘要： An integrated circuit device includes a semiconductor structure, a through-silicon-via (TSV) structure that penetrates through the semiconductor structure and a connection terminal connected to the TSV structure. A metal capping layer includes a flat capping portion that covers the bottom surface of the connection terminal and a wedge-shaped capping portion that is integrally connected to the flat capping portion and that partially covers a side wall of the connection terminal. The metal capping layer may be formed by an electroplating process in which the connection terminal is in contact with a metal strike electroplating solution while a pulse-type current is applied.

公开(公告)号：US09214411B2

公开(公告)日：2015-12-15

申请号：US14506930

申请日：2014-10-06

申请人： Jae-Hwa Park ,  Kwang-jin Moon ,  Suk-Chul Bang ,  Byung-Iyul Park ,  Jeong-gi Jin ,  Tae-seong Kim ,  Sung-hee Kang

发明人： Jae-Hwa Park ,  Kwang-jin Moon ,  Suk-Chul Bang ,  Byung-Iyul Park ,  Jeong-gi Jin ,  Tae-seong Kim ,  Sung-hee Kang

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/485 ,  H01L23/50 ,  H01L21/768 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L23/481 ,  H01L21/6835 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/485 ,  H01L23/49827 ,  H01L23/4985 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/18 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05025 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/14511 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/01047 ,  H01L2924/00

摘要： Integrated circuit (IC) devices are provided including: a first multi-layer wiring structure including a plurality of first wiring layers in a first region of a substrate at different levels and spaced apart from one another, and a plurality of first contact plugs between the plurality of first wiring layers and connected to the plurality of first wiring layers; a through-silicon via (TSV) landing pad including a first pad layer in a second region of the substrate at a same level as that of at least one first wiring layer from among the plurality of first wiring layers, and a second pad layer at a same level as that of at least one first contact plug from among the plurality of first contact plugs and contacts the first pad layer; a second multi-layer wiring structure on the TSV landing pad; and a TSV structure that passes through the substrate and is connected to the second multi-layer wiring structure through the TSV landing pad.

摘要翻译： 提供集成电路（IC）装置，包括：第一多层布线结构，其包括在不同层级并彼此间隔开的基板的第一区域中的多个第一布线层，以及多个第一接触塞 多个第一布线层并连接到多个第一布线层; 贯穿硅通孔（TSV）着陆焊盘，其包括在与所述多个第一布线层中的至少一个第一布线层相同水平的所述基板的第二区域中的第一焊盘层;以及第二焊盘层， 与所述多个第一接触插塞中的至少一个第一接触插塞的水平相同，并接触所述第一衬垫层; TSV着陆板上的第二层多层布线结构; 以及TSV结构，其通过所述基板，并且通过所述TSV着陆焊盘与所述第二多层布线结构连接。

公开(公告)号：US20140070426A1

公开(公告)日：2014-03-13

申请号：US13926616

申请日：2013-06-25

申请人： Jae-hwa Park ,  Kwang-jin Moon ,  Byung-Iyul Park

发明人： Jae-hwa Park ,  Kwang-jin Moon ,  Byung-Iyul Park

IPC分类号： H01L23/48 ,  H01L21/48

CPC分类号： H01L23/481 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L23/53238 ,  H01L23/552 ,  H01L25/0657 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/13 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： Integrated circuit devices are provided. The integrated circuit devices may include a via structure including a conductive plug, a conductive barrier layer spaced apart from the conductive plug, and an insulating layer between the conductive plug and conductive barrier layer. Related methods of forming integrated circuit devices are also provided.

摘要翻译： 提供集成电路设备。 集成电路器件可以包括通孔结构，其包括导电插塞，与导电插塞间隔开的导电阻挡层，以及在导电插塞和导电阻挡层之间的绝缘层。 还提供了形成集成电路器件的相关方法。

公开(公告)号：US08426308B2

公开(公告)日：2013-04-23

申请号：US13235717

申请日：2011-09-19

申请人： Kyu-hee Han ,  Sang-hoon Ahn ,  Jang-hee Lee ,  Jong-min Beak ,  Kyoung-hee Kim ,  Byung-Iyul Park ,  Byung-hee Kim

发明人： Kyu-hee Han ,  Sang-hoon Ahn ,  Jang-hee Lee ,  Jong-min Beak ,  Kyoung-hee Kim ,  Byung-Iyul Park ,  Byung-hee Kim

IPC分类号： H01L21/28 ,  H01L21/44 ,  H01L23/528

CPC分类号： H01L23/481 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76898 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A method of forming through silicon vias (TSVs) includes forming a primary via hole in a semiconductor substrate, depositing low-k dielectric material in the primary via hole, forming a secondary via hole by etching the low-k dielectric in the primary via hole, in such a manner that a via insulating layer and an inter metal dielectric layer of the low-k dielectric layer are simultaneously formed. The via insulating layer is formed of the low-k dielectric material on sidewalls and a bottom surface of the substrate which delimit the primary via hole and the inter metal dielectric layer is formed on an upper surface of the substrate. Then a metal layer is formed on the substrate including in the secondary via hole, and the metal layer is selectively removed from an upper surface of the semiconductor substrate.

摘要翻译： 通过硅通孔（TSV）形成的方法包括在半导体衬底中形成初级通孔，在初级通孔中沉积低k介电材料，通过蚀刻主通孔中的低k电介质形成次级通孔 以同时形成低k电介质层的通孔绝缘层和金属间介电层的方式。 通孔绝缘层由侧壁上的低k电介质材料和限定初级通孔的衬底的底表面形成，并且金属介电层形成在衬底的上表面上。 然后在包括在二次通孔中的基板上形成金属层，并且从半导体基板的上表面选择性地去除金属层。