公开(公告)号：US11410952B2

公开(公告)日：2022-08-09

申请号：US16923574

申请日：2020-07-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Tsung Yen ,  Jhe-Ching Lu ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Min-Chie Jeng

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above the die, or both. The micro bump layer comprises at least one micro-bump line. A filter comprises the electrically conductive layer. A capacitor comprises an electrode formed in the electrically conductive layer.

公开(公告)号：US10521538B2

公开(公告)日：2019-12-31

申请号：US15335091

申请日：2016-10-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Cheng Hsiao ,  Chang-Yu Huang ,  Juan Yi Chen ,  Ke-Wei Su ,  Chung-Kai Lin ,  Lester Chang ,  Min-Chie Jeng

IPC: H01J37/32 ,  G06F17/50 ,  G06F7/58

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

公开(公告)号：US20140278197A1

公开(公告)日：2014-09-18

申请号：US13864376

申请日：2013-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

Inventor： Hsiao-Tsung Yen ,  Chin-Wei Kuo ,  Chih-Yuan Chang ,  Min-Chie Jeng

IPC: G01R31/26 ,  H01L21/66

CPC classification number: H01L22/30 ,  G01R31/2607 ,  G01R31/27 ,  H01L22/34

Abstract: Some embodiments relate to a wafer. The wafer includes a first dummy component comprising two or more first dummy component transmission lines. One of the first dummy component transmission lines operably couples a first signal test pad to a second signal test pad, and an other of the first dummy component transmission lines operably couples a third signal test pad to a fourth signal test pad. A second dummy component comprises two or more second dummy component transmission lines. One of the second dummy component transmission lines operably couples a fifth signal test pad to a sixth signal test pad, and an other of the second dummy component transmission lines operably couples a seventh signal test pad to an eighth signal test pad. Other embodiments are also disclosed.

Abstract translation: 一些实施例涉及晶片。 该晶片包括包含两个或更多个第一虚拟部件传输线的第一虚拟部件。 第一虚拟部件传输线之一可操作地将第一信号测试焊盘耦合到第二信号测试焊盘，并且第一虚设部件传输线中的另一个可操作地将第三信号测试焊盘耦合到第四信号测试焊盘。 第二虚拟部件包括两个或更多个第二虚拟部件传输线。 第二虚拟部件传输线之一可操作地将第五信号测试焊盘耦合到第六信号测试焊盘，并且第二虚设部件传输线中的另一个可操作地将第七信号测试焊盘耦合到第八信号测试焊盘。 还公开了其他实施例。

公开(公告)号：US20210082848A1

公开(公告)日：2021-03-18

申请号：US17098602

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Wei Kuo ,  Hsiao-Tsung Yen ,  Min-Chie Jeng ,  Yu-Ling Lin

IPC: H01L23/00 ,  H01L23/525 ,  H01L23/498 ,  H01L23/66 ,  H01L23/522 ,  H01L21/56 ,  H01L25/065

Abstract: Methods and apparatus for forming a semiconductor device package with a transmission line using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, formed between a top device and a bottom device. A signal transmission line may be formed using a micro-bump line above a bottom device. A ground plane may be formed using a redistribution layer (RDL) within the bottom device, or using additional micro-bump lines. The RDL formed ground plane may comprise open slots. There may be RDLs at the bottom device and the top device above and below the micro-bump lines to form parts of the ground planes.

公开(公告)号：US20200125782A1

公开(公告)日：2020-04-23

申请号：US16721255

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Cheng Hsiao ,  Chang-Yu Huang ,  Juan Yi Chen ,  Ke-Wei Su ,  Chung-Kai Lin ,  Lester Chang ,  Min-Chie Jeng

IPC: G06F30/39 ,  G06F7/58 ,  G06F30/367

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

公开(公告)号：US10216879B1

公开(公告)日：2019-02-26

申请号：US15682863

申请日：2017-08-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Shun Huang ,  Wai-Kit Lee ,  Ya-Chin Liang ,  Cheng Hsiao ,  Juan-Yi Chen ,  Li-Chung Hsu ,  Ting-Sheng Huang ,  Ke-Wei Su ,  Chung-Kai Lin ,  Min-Chie Jeng

IPC: G06F17/50 ,  G06F17/30 ,  H01L21/66

Abstract: A method for establishing an aging model of a device is provided. The device is measured to obtain degradation information of the device under an operating condition, wherein the device is a physical device. The degradation information is partitioned into a permanent degradation portion and an impermanent degradation portion. The impermanent degradation portion is differentiated by time to obtain a differential value. The aging model is obtained according to the differential value. When the differential value is greater than zero, a degradation of the device increases over time, and when the differential value is less than zero, the degradation of the device decreases over time.

公开(公告)号：US08941212B2

公开(公告)日：2015-01-27

申请号：US13760551

申请日：2013-02-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Tsung Yen ,  Cheng-Wei Luo ,  Chin-Wei Kuo ,  Min-Chie Jeng

IPC: H01L21/84 ,  H01L27/08 ,  H01L21/82

CPC classification number: H01L27/08 ,  H01F17/0013 ,  H01F2017/002 ,  H01F2017/0086 ,  H01L21/82 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/0566 ,  H01L2224/06181 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/15311 ,  H01L2924/19015 ,  H01L2924/19042 ,  H01L2924/00

Abstract: The present disclosure relates to a multi-level integrated inductor that provides for a good inductance and Q-factor. In some embodiments, the integrated inductor has a first inductive structure with a first metal layer disposed in a first spiral pattern onto a first IC die and a second inductive structure with a second metal layer disposed in a second spiral pattern onto a second IC die. The first IC die is vertically stacked onto the second IC die. A conductive interconnect structure is located vertically between the first and second IC die and electrically connects the first metal layer to the second metal layer. The conductive interconnect structure provides for a relatively large distance between the first and second inductive structures that provides for an inductance having a high Q-factor over a large range of frequencies.

Abstract translation: 本公开涉及提供良好的电感和Q因子的多电平集成电感器。 在一些实施例中，集成电感器具有第一电感结构，其中第一金属层以第一螺旋图案设置在第一IC管芯上，第二电感结构具有以第二螺旋图案设置在第二IC管芯上的​​第二金属层。 第一IC芯片垂直堆叠在第二IC芯片上。 导电互连结构垂直地位于第一和第二IC芯片之间并将第一金属层电连接到第二金属层。 导电互连结构提供在第一和第二电感结构之间相对较大的距离，其提供在大范围频率上具有高Q因子的电感。

公开(公告)号：US10860769B2

公开(公告)日：2020-12-08

申请号：US16721255

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Katherine Chiang ,  Cheng Hsiao ,  Chang-Yu Huang ,  Juan Yi Chen ,  Ke-Wei Su ,  Chung-Kai Lin ,  Lester Chang ,  Min-Chie Jeng

IPC: G06F30/39 ,  G06F30/367 ,  G06F7/58

Abstract: An integrated circuit (IC) design method includes receiving a spatial correlation matrix, R, of certain property of post-fabrication IC devices; and deriving a random number generation function g(x, y) such that random numbers for a device at a coordinate (x, y) can be generated by g(x, y) independent of other devices, and all pairs of random numbers satisfy the spatial correlation matrix R. The method further includes receiving an IC design layout having pre-fabrication IC devices, each of the pre-fabrication IC devices having a coordinate and a first value of the property. The method further includes generating random numbers using the coordinates of the pre-fabrication IC devices and the function g(x, y); deriving second values of the property by applying the random numbers to the first values; and providing the second values to an IC simulation tool.

公开(公告)号：US20200258672A1

公开(公告)日：2020-08-13

申请号：US16860337

申请日：2020-04-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiao-Tsung Yen ,  Huan-Neng Chen ,  Yu-Ling Lin ,  Chin-Wei Kuo ,  Mei-Show Chen ,  Ho-Hsiang Chen ,  Min-Chie Jeng

IPC: H01F27/28 ,  H01L23/522 ,  H01F17/00

Abstract: A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.

公开(公告)号：US09530705B2

公开(公告)日：2016-12-27

申请号：US13864376

申请日：2013-04-17

Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

Inventor： Hsiao-Tsung Yen ,  Chin-Wei Kuo ,  Chih-Yuan Chang ,  Min-Chie Jeng

IPC: G01R31/27 ,  H01L21/66 ,  G01R31/26

CPC classification number: H01L22/30 ,  G01R31/2607 ,  G01R31/27 ,  H01L22/34

Abstract: Some embodiments relate to a wafer. The wafer includes a first dummy component comprising two or more first dummy component transmission lines. One of the first dummy component transmission lines operably couples a first signal test pad to a second signal test pad, and an other of the first dummy component transmission lines operably couples a third signal test pad to a fourth signal test pad. A second dummy component comprises two or more second dummy component transmission lines. One of the second dummy component transmission lines operably couples a fifth signal test pad to a sixth signal test pad, and an other of the second dummy component transmission lines operably couples a seventh signal test pad to an eighth signal test pad. Other embodiments are also disclosed.

Abstract translation: 一些实施例涉及晶片。 该晶片包括包含两个或更多个第一虚拟部件传输线的第一虚拟部件。 第一虚拟部件传输线之一可操作地将第一信号测试焊盘耦合到第二信号测试焊盘，并且第一虚设部件传输线中的另一个可操作地将第三信号测试焊盘耦合到第四信号测试焊盘。 第二虚拟部件包括两个或更多个第二虚拟部件传输线。 第二虚拟部件传输线之一可操作地将第五信号测试焊盘耦合到第六信号测试焊盘，并且第二虚设部件传输线中的另一个可操作地将第七信号测试焊盘耦合到第八信号测试焊盘。 还公开了其他实施例。