公开(公告)号：US11855066B2

公开(公告)日：2023-12-26

申请号：US17743455

申请日：2022-05-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsiang-Tai Lu ,  Shuo-Mao Chen ,  Mill-Jer Wang ,  Feng-Cheng Hsu ,  Chao-Hsiang Yang ,  Shin-Puu Jeng ,  Cheng-Yi Hong ,  Chih-Hsien Lin ,  Dai-Jang Chen ,  Chen-Hua Lin

IPC: H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L23/498 ,  H01L23/522 ,  H01L23/053

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/565 ,  H01L22/20 ,  H01L22/32 ,  H01L23/3135 ,  H01L23/3185 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L21/4857 ,  H01L21/563 ,  H01L22/14 ,  H01L23/053 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/23 ,  H01L24/24 ,  H01L2224/02379 ,  H01L2224/16225 ,  H01L2224/214 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511 ,  Y02P80/30 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.

公开(公告)号：US09372206B2

公开(公告)日：2016-06-21

申请号：US14833950

申请日：2015-08-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

IPC: G01R31/00 ,  G01R1/04 ,  G01R31/28 ,  H01L21/66 ,  G01R31/26 ,  H01L23/00

CPC classification number: G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

Abstract: A package includes a semiconductor chip. The semiconductor chip includes a test pad, and a plurality of microbump pads, wherein each microbump pad of the plurality of microbump pads is electrically connected to the test pad. The package further includes a substrate; and a plurality of microbumps configured to electrically connect the semiconductor chip to the substrate, wherein each microbump of the plurality of microbumps is electrically connected to a corresponding microbump pad of the plurality of microbump pads. The package further includes a package substrate, wherein the package substrate comprises a bump pad, wherein an area of the bump pad is greater than a combined area of the test pad and the plurality of microbump pads. The package further includes a bump configured to electrically connect the substrate to the package substrate.

Abstract translation: 封装包括半导体芯片。 半导体芯片包括测试焊盘和多个微型块焊盘，其中多个微型块焊盘中的每个微型焊盘电连接到测试焊盘。 所述封装还包括衬底; 以及多个微胶片，其被配置为将所述半导体芯片电连接到所述基板，其中所述多个微胶片中的每个微小块电连接到所述多个微型块衬垫中的对应的微型块体。 封装还包括封装衬底，其中封装衬底包括凸块焊盘，其中凸块焊盘的面积大于测试焊盘和多个微型块焊盘的组合面积。 所述封装还包括凸起，所述凸起被配置为将所述衬底电连接到所述封装衬底。

公开(公告)号：US10741537B2

公开(公告)日：2020-08-11

申请号：US15725766

申请日：2017-10-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsiang-Tai Lu ,  Shuo-Mao Chen ,  Mill-Jer Wang ,  Feng-Cheng Hsu ,  Chao-Hsiang Yang ,  Shin-Puu Jeng ,  Cheng-Yi Hong ,  Chih-Hsien Lin ,  Dai-Jang Chen ,  Chen-Hua Lin

IPC: H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L23/498 ,  H01L23/522 ,  H01L23/053

Abstract: A method of manufacturing a semiconductor structure includes forming a redistribution layer (RDL); forming a conductive member over the RDL; performing a first electrical test through the conductive member; disposing a first die over the RDL; performing a second electrical test through the conductive member; and disposing a second die over the first die and the conductive member.

公开(公告)号：US20220359315A1

公开(公告)日：2022-11-10

申请号：US17870871

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzuan-Horng Liu ,  Chao-Hsiang Yang ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

公开(公告)号：US11450579B2

公开(公告)日：2022-09-20

申请号：US17207736

申请日：2021-03-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzuan-Horng Liu ,  Chao-Hsiang Yang ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L21/66 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

公开(公告)号：US20210210395A1

公开(公告)日：2021-07-08

申请号：US17207736

申请日：2021-03-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzuan-Horng Liu ,  Chao-Hsiang Yang ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

公开(公告)号：US20240087967A1

公开(公告)日：2024-03-14

申请号：US18513649

申请日：2023-11-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzuan-Horng Liu ,  Chao-Hsiang Yang ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L22/32 ,  H01L23/3157 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0217 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/06515 ,  H01L2224/13007

Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

公开(公告)号：US11869819B2

公开(公告)日：2024-01-09

申请号：US17870871

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzuan-Horng Liu ,  Chao-Hsiang Yang ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L21/66 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L22/32 ,  H01L23/3157 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0217 ,  H01L2224/0401 ,  H01L2224/05556 ,  H01L2224/06515 ,  H01L2224/13007

Abstract: An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

公开(公告)号：US11335672B2

公开(公告)日：2022-05-17

申请号：US16937343

申请日：2020-07-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsiang-Tai Lu ,  Shuo-Mao Chen ,  Mill-Jer Wang ,  Feng-Cheng Hsu ,  Chao-Hsiang Yang ,  Shin-Puu Jeng ,  Cheng-Yi Hong ,  Chih-Hsien Lin ,  Dai-Jang Chen ,  Chen-Hua Lin

IPC: H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L23/498 ,  H01L23/522 ,  H01L23/053

Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.

公开(公告)号：US09116203B2

公开(公告)日：2015-08-25

申请号：US14331791

申请日：2014-07-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Cheng Wu ,  Hsien-Pin Hu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Chen-Hua Yu ,  Chao-Hsiang Yang

IPC: G01R31/00 ,  G01R31/28 ,  H01L21/66 ,  H01L23/00

CPC classification number: G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

Abstract: A test structure including an array of microbumps electrically connecting a chip and a substrate, wherein a width of each microbump of the array of microbumps is equal to or less than about 50 microns (μm). The test structure further includes an interconnect structure connected to the array of microbumps. The test structure further includes an array of test pads around a periphery of the array of microbumps, wherein a test pad of the array of test pads is connected to a corresponding microbump of the array of microbumps through the interconnect structure. A width of the test pad is greater than a width of the corresponding microbump, and the test pad is adapted to be covered after circuit probing by a passivation material to prevent particle and corrosion issues.

Abstract translation: 一种测试结构，其包括将芯片和基板电连接的微型阵列阵列，其中微胶片阵列的每个微型块的宽度等于或小于约50微米（μm）。 测试结构还包括连接到微丸阵列的互连结构。 该测试结构进一步包括围绕微胶片阵列周边的测试焊盘的阵列，其中测试焊盘阵列的测试焊盘通过互连结构连接到微胶片阵列的对应微型块。 测试垫的宽度大于对应的微型块的宽度，并且测试垫适于在通过钝化材料的电路探测之后被覆盖以防止颗粒和腐蚀问题。